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Logic encryption is a popular technique to safeguard an IC design from different security vulnerabilities. However, several recently proposed attacks can extract the secret keys of an encrypted design. In this paper, we propose a new logic encryption strategy, which integrates an additional key generation unit with the design. The key generation unit takes external keys and performs a permutation...
A novel Denial-of-Service attack for Networks-on-Chip, namely illegal packet request attack (IPRA), has been proposed and measures to mitigate the same have been addressed. Hardware Trojans, which cause these attacks, are conditionally triggered inside the routers at the buffer sites associated with local core, when the core is idle. These attacks contribute to the degradation of network performance...
With the globalization of IC design flow, many fabless companies outsource the fabrication of their design to off-site foundries. As these foundries may not always be trusted, it results in security vulnerabilities and threats such as counterfeiting, IP piracy, reverse engineering, overbuilding and Hardware Trojans. Logic encryption has emerged to be a potential solution to secure the design against...
The IEEE 1687 Standard specifies an access network and a description language for embedded instruments. In this paper, we present an optimization technique to minimize the segment insertion bit (SIB) programming overhead for IEEE 1687-compliant access architectures. We first present an optimal solution based on dynamic programming for concurrent access schedules. This technique is then utilized to...
Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. Limited observability due to test response compaction negatively affects the diagnosis procedure. When multiple chains, mapped to a single compactor, fail, diagnosis becomes extremely difficult. The procedure is even more complicated because when...
Accuracy of any diagnosis algorithm depends on the test set used. Test that is able to distinguish more fault pairs is better suited for aiding diagnosis. Standard detection test set is generated to detect faults using less number of test patterns. It is unable to distinguish many fault pairs. To distinguish pairs, more patterns are required that consumes ATE memory and time. In this work we devised...
Temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a particle swarm optimization (PSO) based test pattern generation strategy has been proposed for BIST environment...
With rapid progress in VLSI technology, temperature during testing has become a big issue. As increase in temperature during testing causes permanent or temporal damage of the chip, reduction in peak temperature of the chip becomes necessary. Temperature depends on both heat generation caused by power consumption and heat dissipation among neighboring blocks in the circuit under test (CUT). Heat generation...
Volume Diagnosis is extremely important to ramp up the yield during the IC manufacturing process. Limited observability due to test response compaction negatively affects the diagnosis procedure. Hence, in a compaction environment, it is important to implement Design For Diagnosis (DFD) methodology to restore diagnostic resolution. In this paper, a novel DFD technique which makes the faulty chains...
In the sub 70 nm technologies, the leakage power dominates dynamic power. Most of the power calculation methods account for dynamic power dissipation and static leakage power dissipation, but the runtime leakage is generally neglected. It has been shown in recent studies that the contribution of runtime leakage power to the total power dissipation is not negligible any more. The dynamic power dissipation...
In this paper we present a method to identify don't care locations in a fully specified set of vectors, considering both fault propagation path and fault activation path. We exploit the identified X bits to convert the original vector to low power vector by dictionary based approach to minimize both dynamic and runtime leakage power. The dynamic power as well as the runtime leakage power depends on...
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