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As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured ASICs can offer price and performance between ASICs and FPGAs. They are attractive for mid-volume production and offer good intellectual property security. In this paper, a structured ASIC methodology, where 2 metal- and 1 via-mask are customised, is described. The CAD tools are fully...
A Structured Application-specific Integrated Circuit (SASIC) is a programmable fabric in which a small set of masks are customized for a particular application, serving to reduce the associated non-recurring engineering cost (NRE). In this paper we describe the implementation of a SASIC logic cell which is programmable via a single metal layer. A SASIC fabric prototype is fabricated and all implemented...
We describe the architecture of a structured ASIC fabric in which the logic and routing can be customized using three masks. A standard Cadence based design flow is employed, and using an active dynamic backlight controller as an example, performance is compared to that of an ASIC implementation in the same technology.
This paper presents a low-power, passive, UHF RFID tag design compatible with EPCTM C1G2 protocol. In order to reduce its cost, diode-connected NMOS in a standard CMOS technology is used instead of Schottky diodes. With the help of low-threshold-voltage, triple-well NMOS, a minimum input power of -7.6 dBm is achieved. A sub-1 V, low temperature-coefficient voltage reference using self-biased mutual...
A voltage multiplier for passive RFID tags is designed in a 0.35-μm 2-poly 4-metal CMOS technology. Due to the limitations of the technology, an optimized design is difficult to achieve easily. Based on some design studies, an voltage multiplier working at 13.5 MHz is developed and realized on silicon. From the measurement, the output voltage is about 2.5 V and the output current is 6.4 μA. when an...
In this paper, an electrocardiographic (ECG) signal processing IC, which is used for portable biomedical application, was designed using continuous-time technique. The circuit consists of an instrumentation amplifier (INA) with driven-right-leg circuit (DRL), a 5th order Gm -C low pass filter (Gm-C LPF) operating in sub-threshold mode, and amplifiers. DRL circuit is used to detect small amplitude...
In this paper, a CMOS low noise amplifier (LNA) employing the switched-capacitors is proposed to perform multi-band tuning for an MB-OFDM ultra-wideband (UWB) hopping system. By using the fully differential topology, the switching noise generated during each frequency transition interval is greatly suppressed. The proposed UWB LNA is implemented in a standard 0.18-mum CMOS process. The simulation...
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