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A new model of electrostatic discharge (ESD) event is found in ICs during chip-on-film (COF) package. The behavior of this new kind of ESD is different from the human-body mode (HBM), machine model (MM) and charge device model (CDM) model. We call it the charge tape model (CTM). It often damages the gate oxides of the input circuit and output circuit in IC to result in the yield loss. The mechanism...
The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip...
Ring-type yield loss at wafer edge has been observed during flip-chip packaging process. The failure mechanism is attributed to the scrubber clean process step which generates a lot of charges. This in turn behaves like an electrostatic discharge (ESD) event and damages gate oxide of internal circuits. An equivalent circuit is proposed to analyze such a kind of ESD event and proves the importance...
A novel ESD device structure with non-LDD at drain region has been demonstrated to enhance the ESD immunity of IO circuits with mixed high/low operation voltage. The protection capability of this novel ESD device structure has been proved from 1 mum to 65 nm technologies with and without fully salicide at the source/drain region. This structure is found to be also very effective to protect the high...
This paper describes a process-induced damage phenomenon on the Poly-Insulator-Poly (PIP) capacitor of mixed-mode circuit during the scrubber clean after Spin-On-Glass (SOG) layer deposition. The damage mechanism is the generated charges during the scrubber clean flow through the SOG film, metal-2 stripe, via hole and to dummy metal-1 stripe, and then charge up the parasitic capacitor (dummy metal-1...
This paper investigates the influence of the N-type buried layer (NBL) layout and LOCOS space on the ESD performance and trigger voltage of the lateral DMOS (LDMOS) device. Without adequate LOCOS spacing, LDMOS is vulnerable to ESD damage. If the LOCOS space is sufficiently wide, adding NBL structure can further improve LDMOS ESD performance significantly. This is because NBL can switch the current...
In this paper, the impact of ball bonding (BB) induced voltage transient on the reliability test including electro-migration (EM), time dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) and electro-static discharge (ESD) are investigated. During the electronic flame-off (EFO) of ball bonding process, a spark discharge current, which applies a high electric field between...
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