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The recent research reveals that the bit error rate of a NAND flash cell is highly dependent on the stored data patterns. In this work, we propose Data Pattern Aware (DPA) error protection technique to extend the lifespan of NAND flash based storage systems (NFSS). DPA manipulates the ratio of 1's and 0's in the stored data to minimize occurrence of the data patterns which are susceptible to bit error...
A high-throughput memory-efficient arithmetic coder architecture for the set partitioning in hierarchical trees (SPIHT) image compression is proposed based on a simple context model in this paper. The architecture benefits from various optimizations performed at different levels of arithmetic coding from higher algorithm abstraction to lower circuits' implementations. First, the complex context model...
An efficient implementation of discrete wavelet transform (DWT) in JPEG2000 is designed with low memory and high pipeline architecture. Considering the limited dynamic range of wavelet coefficients, a modified scheme of integer-to-integer discrete wavelet transform based on fixed-point manipulation is proposed by preserving efficiently fractions of coefficients in lifting steps. This scheme ensures...
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