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This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). The proposed comparator reduces the input referred noise by half and shows a better output driving capability when compared with the previous work. The offset, noise and power consumption can be controlled by a clock delay which allows...
This paper presents a topology to improve the system linearity and reduce the complexity of high-speed binary-search ADCs. The proposed topology, when compared with previous binary-search ADC architectures, further reduces the number of comparators from 2N-1 to N for N-bit precision, the comparator structure is simplified, and it can avoid both the signal dependent offsets and the kickback noise....
A clock generation technique for reducing the clock-jitter sensitivity of Switched current (SI) Return-to-Zero (RZ) DAC in CT ΣΔ modulators is presented in this paper. While realizing the clock-jitter insensitivity, this technique ensures that the feedback period can be utilized more efficiently so that the amplitude of feedback current can be reduced. The proposed technique employs simple digital...
This paper proposes a differential switched-capacitor (SC) biquad filter exploiting a hybrid structure. The 1st active core is an operational amplifier (OpAmp) whereas the 2nd is an improved comparator-based circuit (CBC). The advantages of this new structure are justified by the reductions of power and transistor sizes. Optimized in a 65-nm CMOS process, when compared with a typical dual-OpAmp design,...
This paper describes a 90 nm CMOS low-noise low-power biopotential signal readout front-end (RFE). The front-stage instrumentation amplifier (IA) features a chopper; an AC-coupler and a novel chopper notch filter for minimizing the DC-offset; transistors' flicker noise and 50 Hz powerline interference concurrently. A noise-aware transistor selection (thin- and thick-oxide) in the IA enables a flexible...
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