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A dual-mode baseband (W-CDMA/HSDPA and GSM/GPRS/EDGE) and multimedia application processor SoC is described. The SoC fabricated in triple-Vth 65 nm CMOS has 3 CPU cores and 20 separate power domains to achieve both high performance and low power. The SoC adopts the partial clock activation scheme that reduces power by 42% for long-time music replay. The IP-MMU is introduced to reduce maximum memory...
The paper presents a single-chip application and dual-mode baseband processor. It features triple V design - a technology in a low-power 65nm CMOS process that achieves 500MHz for two CPUsp; power domains are separated into 21 sub-blocks to reduce leakage power; introduces a new IP-MMU, which translates virtual address to physical address or physical address to physical address, to 17 different kinds...
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method can achieve very low leakage current in the partial active mode of a single chip mobile processor. The single chip mobile processor embedded three CPU's that is baseband processor, application processor, and multimedia processor...
A power-management scheme for a single-chip multi-CPU processor uses 20 power domains. The scheme enables the minimization of leakage currents in each operating mode: 299muA in paging operation and 7muA in stand-by. The techniques for controlling and implementing power domains are also described
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