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This work proposes a Sum of Absolute Transformed Differences (SATD) architecture based on multiple sizes Hadamard Transforms (HTs) and adder compressors, where the smallest HTs are reused for the implementation of the largest ones. A new adder/subtractor compressor is proposed and used to implement additions and subtractions of the HT module, while conventional 4-2 and 8-2 adder compressors are used...
The HEVC standard brings large gains in coding efficiency, significant increase in computational effort and a new parallel encoding structure called tiles. Tiles can be used to greatly decrease encoding time through parallel processing at the cost of coding efficiency degradation. In multi-core systems running multiple tasks, the resources available to the HEVC application may not remain constant...
The most recent video compression standard is the High Efficient Video Coding (HEVC). It was created with the goal of reaching better videos compression compared to the existing ones. One of the most time-consuming modules of HEVC encoder is the Sum of Absolute Transform Differences (SATD), which is used in intra prediction mode decision and in Fractional pixel Motion Estimation (FME) modules. This...
This work presents an efficient method to map the Full Search algorithm for Motion Estimation (ME) onto General Purpose Graphic Processing Unit (GPGPU) architectures using Compute Unified Device Architecture (CUDA) programming model. Our method jointly exploits the massive parallelism available in current GPGPU devices and the parallelism potential of Full Search algorithm. Our main goal is to evaluate...
This work presents an efficient method to map Motion Estimation (ME) algorithms onto General Purpose Graphic Processing Unit (GPGPU) architectures using CUDA programming model. Our method jointly exploits the massive parallelism available in current GPGPU devices and the parallelization potential of ME algorithms: Full Search (FS) and Diamond Search (DS). Our main goal is to evaluate the feasibility...
In the Rate-Distortion Optimization technique for H.264/AVC, the process of choosing the best mode is performed through exhaustive executions of the whole encoding process, which increases significantly the encoder complexity, sometimes even forbidding its use in real time video coding applications. In order to reduce the number of calculations necessary to determine the best inter-frame mode, this...
In this work we present a high throughput hardware architecture for the H.264/AVC intra-frame encoder exploiting the parallelism of intra prediction, forward and inverse transforms and quantization. Since there is a strong data dependency between the intra prediction and the image reconstruction loop, the latency of this path is a key design issue in order to provide high performance coding. Considering...
This work presents a detailed timing and communication analysis for an H.264/AVC video encoder architecture using a SystemC model. The model was described using different abstraction levels in order to evaluate specific characteristics of each component module. The target encoder is defined to be able for H.264/AVC real-time encoding for 1080p video sequences at 30 fps and was modeled as a two-stage...
Sum of Absolute Difference (SAD) is a low complexity distortion metric widely employed in the mode decision stage of real-time video encoders. In H.264/AVC encoding, the state-of-the-art video coding standard, motion estimation responds for the most computational complexity, most of it coming from the SAD calculation for all the candidate blocks. Considering an H.264/AVC motion estimation hardware...
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