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In this paper, we fabricated an 8-bit SAR ADC with a 16-nm FinFET process. A time-interleaved (TI-) ADC is remarked as an ADC with high speed sampling rate. Considering the area, the power consumption and the complexity of the mismatch calibration, it is possible that a unit SAR ADC of the TI-ADC with higher sampling rate improves these performances. We configure the SAR ADC with the high speed operation...
A 97.99 dB SNDR, 2 kHz bandwidth noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. Distortion due to mismatch of capacitive DAC is eliminated by introducing dynamic element matching (DEM) technique and by utilizing modulation dither effect. The...
A high power efficient and scalable noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. 97.99 dB SNDR and 111.8 dB SFDR for 2 kHz bandwidth with only 37.1 µW power consumption is measured. By increasing sampling frequency, the performance of the...
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