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The tolerance of device morphology in wafer-level bonding through polymer-coated layer was investigated for the application of 3D integration. Several different pillar heights were fabricated on wafers to simulate the case of bonding with real devices on wafers. Overall, the wafer morphology with polymer-coated layer above devices less than 2 μm can achieve excellent bonding quality. Furthermore,...
An ultra-fast temporary bonding and release process was investigated for the improvement of 3D integration. The bonding scheme composes of two different kinds of polymer for release layer and adhesive layer. The submicron release layer is a positive photoresist with the characteristic of high UV absorption induced into the de-bonding procedure within 20 s. In addition, the adhesive layer provides...
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