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We present a detailed-routability driven placement algorithm with fence constraint. It is two-step process involving global placement and detailed placement. Our global placement is an upper-bound-lower-bound optimization framework honoring fence constraint. The lower-bound step is a wirelength-driven analytical placement solved by a box-constrained conjugate gradient (CG) method. The upper-bound...
As technology scales down quickly, timing becomes more and more critical in modern designs. During placement and routing, a lot of techniques are applied to reduce circuit delay. A good timing driven routing tree construction can influence placement and routing significantly. As circuits become more and more complex, previous algorithms may not be efficient enough to be applied in modern designs....
Multiple Patterning Lithography (MPL) is indispensable for producing sub-22nm devices. Recently, multiple patterning with cutting (MPC) was proposed. For example, in triple patterning with cutting (LELECUT), the first two masks are used to do double patterning, whereas the third mask is used to cut off the unwanted parts. In this paper, we will systematically study the problem of cut candidate generation,...
Block Copolymer Directed Self-Assembly (DSA) is a promising technique to print contacts/vias for the 10nm technology node and beyond. By using hybrid lithography that cooperates DSA with multiple patterning, multiple masks are used to print the DSA templates and then the templates can be used to guide the self-assembly of the block copolymer. In this paper, we propose approaches to solve the simultaneous...
Triple patterning lithography (TPL) is attracting more and more attention due to further scaling of the critical feature size. How fully the benefits of TPL can be utilized depends very much on both the decomposition and layout steps. However, it is non-trivial to perform detailed routing and layout decomposition simultaneously on a large-scale complicated circuit to achieve decomposability on one...
In this paper, we focus on the hypergraph bipartitioning problem and present a new multilevel hypergraph partitioning algorithm that is much faster and of similar quality compared with hMETIS. In the coarsening phase, successive coarsened hypergraphs are constructed using the MFCC (Modified First-Choice Coarsening) algorithm. After getting a small hypergraph containing only a small number of vertices,...
Due to a significant mismatch between the objectives of wirelength and routing congestion, the routability issue is becoming more and more important in VLSI design. In this paper, we present a high quality placer Ripple 2.0 to solve the routability-driven placement problem. We will study how to make use of the routing path information in cell spreading and relieve congestion with tangled logic in...
In this paper, we describe a routability-driven placer called Ripple. Two major techniques called cell inflation and net-based movement are used in global placement followed by a rough legalization step to reduce congestion. Cell inflation is performed in the horizontal and the vertical directions alternatively. We propose a new method called net-based movement, in which a target position is calculated...
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