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Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For reprint or republication permission,...
In the conventional ASIC design flow, slew constraints are imposed on clock sinks and clock buffers uniformly. The slew constraint has a significant affect not only on the timing but also on power in high performance designs. This paper investigates relaxing tight slew constraints for the reduction of low-impact buffers in clock trees. This is motivated by the observation that buffers in a clock tree that...
Modern VLSI systems are limited by power constraints, and many solutions exists to reduce power consumption. In static CMOS energy is dissipated by the pull-up and pull-down networks during low-to-high and high-to-low transitions, respectively. The charge is moved from the power source to the load capacitance, then discharged to ground. Charge recovery logic (CRL) saves energy by recovering, or recycling,...
The Integrated Circuit (IC) industry is approaching an important transition. For decades, the persistent downscaling of feature sizes has enabled a rapidly growing integration and exponentially increasing circuit performance. But process variations and device aging are posing increasingly serious challenges to the sustainability of the current development model of integrated circuits. Accordingly,...
Heterogeneous integration of disparate device planes is a benefit of through-silicon-via based 3-D integrated circuits (ICs). Clock delivery for heterogeneous 3-D ICs requires novel circuit techniques and algorithms as compared to 2-D and even homogeneous 3-D ICs. Novel algorithms for topology generation (heterogeneous 3-D balanced bipartitioning) and for embedding of a clock tree in a heterogeneous...
We present a detailed-routability driven placement algorithm with fence constraint. It is two-step process involving global placement and detailed placement. Our global placement is an upper-bound-lower-bound optimization framework honoring fence constraint. The lower-bound step is a wirelength-driven analytical placement solved by a box-constrained conjugate gradient (CG) method. The upper-bound...
As technology scales down quickly, timing becomes more and more critical in modern designs. During placement and routing, a lot of techniques are applied to reduce circuit delay. A good timing driven routing tree construction can influence placement and routing significantly. As circuits become more and more complex, previous algorithms may not be efficient enough to be applied in modern designs....
In this paper, we propose a three-stage reconfigurable topology synthesis approach for Application-Specific NoC (ASNoC) on partially dynamically reconfigurable FPGAs, where the topology is reconfigured dynamically at run-time along with the application’s execution. Firstly, given the scheduling and floorplanning of task modules, an Integral Linear Programming (ILP)-based method is proposed to partition...
Silicon photonic interconnects are being considered for integration in future networks-on-chip (NoCs) as they can enable higher bandwidth and lower latency data transfers at the speed of light. Such photonic interconnects consist of photonic waveguides with dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation and detection. To enable...
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