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This work evaluates the SEE static and dynamic sensitivity of a single-chip many-core processor having implemented 16 compute clusters, each one with 16 processing cores. The SEU error-rate of an application implemented in the device is predicted by combining experimental results with those issued from fault injection campaigns applying the CEU (Code Emulating Upsets) approach. In addition, a comparison...
MPSoC architectures bring flexibility and performance, but to avoid high power consumption, they still require a careful design. When taking into account variability in advanced CMOS technologies, individual optimization of each chip is necessary. In this paper, we present an approach based on Game Theory to address this issue at run-time in a distributed way, frequencies are dynamically adjusted...
Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing performance with real-time constraints, low-power consumption and low cost. With the rapid evolution of telecom standards and the increasing demand for multi-standard products, the need for flexible baseband solutions is growing...
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