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We present numerical simulations of thermal phenomena in SOI MOSFETs flip-chip packages. We consider the effects of package environment on isolated transistors performing multi-scale Finite Elements thermal simulations. Furthermore, we perform a complete thermal analysis of a microchip in a flip-chip package. We build a robust Finite Elements model of a typical ten-level Back End of Line (BEoL) in...
Coupled effects of substrate orientation and germanium concentration during silicon-germanium Solid Phase Epitaxial Regrowth (SPER) is analyzed through lattice kinetic Monte Carlo simulations. Atomistic events depending on the bonding environment allow to replicate the effects of alloying on SPER velocity of (100) substrates. The model is then used to draw predictions of the regrowth anisotropy in...
WLCSP (Wafer Level Chip Scale Packaging) is used to enable low-cost manufacturing and a high performance featuring low I/O density. Such a solution provides a solder interconnection directly between the die and motherboard. This paper aims at presenting the specificities of this new assembly by describing the most common thermo-mechanical failures encountered and by proposing some containment solutions...
Among the numerous ways to process 3D stacking of integrated circuits, a promising method is the use of Cu/SiO2 hybrid bonding, which enables simultaneous mechanical and electrical connections with an interconnection pitch limited only by photolithography resolution and alignment accuracy. In this work, we present a finite element model of the bonding of Cu/SiO2 patterned surfaces with the aim of...
Process complexity of advanced CMOS technologies interconnect increases continuously in the uninterrupted move towards miniaturization and verticalization. In the same time the window market of new more complex consumer products are shrinking faster and faster. This paper gives a comprehensive description of the most relevant and advanced methodologies and tools carried out to achieve quickly a yielding...
The effects of different surface preparations on NiPtSi thermal stability were studied. HF wet clean, argon sputter etch and remote plasma pre-clean were used as silicide pre-cleans prior to NiPt sputter deposition and subsequent silicidation on blanket and patterned Si wafers. NiPtSi was characterized using SIMS, ellipsometry, voltage contrast (ES25) testing and electrical performance measurements...
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