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In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the...
In this paper, a single-precision floating-point FFT Twiddle Factor (TF) implementation is proposed. The architecture is based on Adaptive Angle Recoding CORDIC (AARC) algorithm. The TF design is built and verified on Altera Stratix IV FPGA chip and 65nm SOTB synthesis. The FPGA implementation has 103.9 MHz maximum frequency, throughput result of 16.966 Mega-Sample per second (MSps), and resources...
In this paper, the authors proposed highperformance DCT architectures based on Coordinate Rotation Digital Computer (CORDIC). The implementations deployed Adaptive angle recoding CORDIC (ACor) method and Scale-Free Factor (SFF) technique. There are two models presented in the paper: ACor-based Chen-DCT (ACor-DCT-C) and ACor-based Loeffler-DCT (ACor-DCT-L). The critical path in both models is six adder-delay...
In this paper, a hybird adaptive Coordinate Rotation Digital Computer (HA-CORDIC) has implemented in 65nm Silicon On Thin Buried oxide (SOTB) CMOS technology. In the HA-CORDIC implementation, the adaptive algorithm is utilized for reducing the iteration of CORDIC algorithm. In comparison with other floating-point CORDIC designs, the latency of our proposed scheme is lower. It spends only 12, 20, and...
Recent years have witnessed a massive growth of global data due to the ubiquitous internet-of-thing products, social networking services, and mobile devices. Fast database analytics, therefore, has been increasingly attractive to numerous research. In this paper, a low-latency FPGA-based Database Processor (DBP) using bitmap index is proposed. By exploiting available embedded memory blocks and logic...
Coordinate Rotation Digital Computer (CORDIC) was an efficient algorithm to compute elementary arithmetic such as multiplication, division, and root extractions. However, conventional CORDIC algorithm requires high latency to obtain the results. This paper proposes a low latency parallel pipeline CORDIC (PP-CORDIC) to calculate trigonometric functions. The results show that PP-CORDIC can operate at...
In this paper, a low-resource low-latency hybrid adaptive COordinate Rotation DIgital Computer (HA-CORDIC) is implemented both in FPGA and 180-nm CMOS technology. The adaptive algorithm reduces around 50% iterations in comparison with the conventional CORDIC algorithm. The hybrid architecture together with resource sharing, parallel and pipeline processing are utilized in HA-CORDIC implementation...
The delay of the multiplier plays a critical role in many high-speed implementations and processors such as RISC, DSP, and image processing cores, etc. In this paper, a design of unsigned 32-bit multiplier is proposed, aiming to achieve the best timing performance with an appropriate area. The proposed architecture consists of a modified Radix-4 Booth encoder, a modified Wallace Tree adder, and a...
Image segmentation is an indispensable first step in many image processing tasks. Many attempts have been made over the time including traditionally approaches (i.e. threshold-based, edge-based, and region growing) to modern methods of machine learning and neural networks. However, the final solution hasn't be found as yet. Recently, the Local Excitatory Global Inhibitory Oscillator Network (LEGION)...
Nowadays, IP watermarking becomes the state-of-the-art technique in the field of IP protection. This technique aims at implanting a message such as a signature into the structure without changing the original functionality. One of the mainstreams of IP watermarking research is the Finite State Machines (FSM) watermarking. In this paper, we propose two FSM watermarking techniques which embed a signature...
Although the advancement in Intellectual Property (IP) design increases rapidly, it is easy to copy and resell IP cores without noticing its owners. As a consequence, IP Protection (IPP) using watermarking has emerged as the state-of-the-art technique and raises numerous interests from many Integrated Circuit (IC) designers. In this paper, we propose a constraints-based watermarking technique to embed...
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