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This paper presents a simulation-based analysis of spike and flicker noise in a Phase Change Memory (PCM); this investigation is based on HSPICE simulation by taking into account cell-level (with its neighbors) and array-level considerations. State switching phenomena in binary PCM memories are dealt in detail to assess the impact of these two types of noise. It is shown that a lower feature size...
Approximate circuit design is an innovative paradigm for error-resilient image and signal processing applications. Multiplication is often a fundamental function for many of these applications. In this paper, three approximate compressors are proposed with an accuracy constraint for the partial product reduction (PPR) in a multiplier. Both approximation and truncation are considered in the approximate...
This paper introduces the HSPICE macromodel of a racetrack memory (also commonly known as a domain-wall memory). MATLAB is used to generate the HSPICE code and different features of a perpendicular magnetic anisotropy (PMA) racetrack memory are evaluated. The proposed model simulates the write, the read and the shift operations of a racetrack memory. A good agreement between the simulation results...
Different schemes for approximate computing of matrix multiplication (MM) in systolic arrays are presented in this manuscript. Inexact full adder cells are utilized in a processing element (PE) for the Baugh-Wooley multiplier and/or the final adder as circuits implementing the two computational steps required for MM. An extensive analysis and simulation-based assessment of three inexact schemes for...
Power dissipation has become a significant concern for integrated circuit design in nanometric CMOS technology. To reduce power consumption, approximate implementations of a circuit have been considered as a potential solution for applications in which strict exactness is not required. In approximate computing, power reduction is achieved through the relaxation of the often demanding requirement of...
This paper deals with a so-called racetrack memory (also commonly known as a domain-wall memory). Novel circuits for implementing the write, the read and the shift operations of the racetrack cell are introduced; the proposed circuits are very efficient in terms of numerous figures of merit, such as delay, power dissipation, and power delay product (PDP). An extensive analysis of variation in the...
Memory design has radically changed in the last few years; the emergence of new technologies has further improved performance and the traditional separation of storage levels between Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is not viable as in the past. Recently, the embedded DRAM (eDRAM) has been proposed for cache utilization to improve density while attempting...
This paper relies on the principles of inexact computing to alleviate the issues arising in static masking by voting for reliable computing. A scheme that utilizes approximate voting is proposed; it is referred to as inexact double modular redundancy (IDMR). IDMR does not resort to triplication, thus saving overhead due to modular replication; moreover, this scheme is adaptive in its operation, i...
This paper presents a method for operational testing of a memristor-based memory look-up table (LUT). In the proposed method, the deterioration of the memristors (as storage elements of a LUT) is modeled based on the reduction of the resistance range as observed in fabricated devices and recently reported in the technical literature. A quiescent current technique is used for testing the memristors...
Approximate computing is best suited for error resilient applications, such as signal processing and multimedia. Approximate computing reduces accuracy, but it still provides meaningful and faster results with usually lower power consumption, this is particularly attractive for arithmetic circuits. In this paper, a new design approach is proposed to exploit the partitions of partial products using...
This paper presents a novel scheme for a memristor-based look-up table (LUT); in this scheme the states of the unselected memristors are unaffected by WRITE/READ operations. Therefore, it addresses the prevalent problems associated with nano crossbars, such as the write half-select and sneak path currents. In the proposed scheme the memristors are connected in rows and columns, while the columns are...
This paper presents a system-level scheme to alleviate the effect of resistance drift in a multilevel phase change memory (PCM) for data integrity. In this paper, novel criteria of separation of the PCM resistance for multilevel cell storage and selection of the threshold resistances between levels are proposed by using a median based method based on a row of PCM cells as reference. The threshold...
This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. Simulation of these cells shows that their operation...
This paper proposes a new macromodel that takes into account the threshold switching and the resistance recovery processes in addition to the drift behavior of a Phase Change Memory (PCM). Simulation results are provided for both DC and drift behaviors; they show that the proposed macromodel is very accurate at a small error when compared with data from experimental devices. A sensitivity analysis...
The silicon-on-insulator (SOI) MOSFET is considered as an alternative to the bulk (silicon-based MOSFET in CMOS circuits for applications requiring low-voltage and low-power operation. Fully depleted SOI (FDSOI) benefits from a high current driven ability; so, this technology preserves advantageous features, such as steep sub threshold characteristics and small short channel effects. This paper presents...
This paper analyzes and improves the performance of a hybrid memory cell consisting of a memristor and ambipolar transistors. This work extends a previous design by efficiently biasing the memristor (as controlled by the ambipolar transistors), such that no refresh operation is now required. By utilizing macroscopic models, the features of the cell are characterized for the memory operations and no...
Power has become a key constraint in current nanoscale integrated circuit design due to the increasing demands for mobile computing and a low carbon economy. As an emerging technology, an inexact circuit design offers a promising approach to significantly reduce both dynamic and static power dissipation for error tolerant applications. Although fixed-point arithmetic circuits have been studied in...
This paper presents a Ternary Content Addressable Memory (TCAM) cell that employs memristors as storage element. The TCAM cell requires two memristors in series to perform the traditional memory operations (read and write) as well as the search and matching operations for TCAM; this memory cell is analyzed with respect to different features (such as memristance range and voltage threshold) of the...
This paper presents a new HSPICE macromodel of a Programmable Metallization Cell (PMC). The electrical characteristics of a PMC are simulated by using a geometric model that considers the vertical and lateral growth/dissolution of the metallic filament. The selection of the parameters is based on operational features, so the electrical characterization of the PMC is simple, easy to simulate and intuitive...
This paper presents a memristor-based Look-Up Table (LUT) for FPGAs. The proposed memory utilizes memristors as storage elements and NMOS transistors for selection. New WRITE and READ operations are proposed; the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation for both the word and bit lines. Also, it requires a RESTORE pulse only for the READ 0 operation. The WRITE...
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