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In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to less than 5 μm for light detection from the backside...
In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside...
The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed...
On one hand, with the rapid increase of integrated circuits (ICs) I/O number, the traditional package technique does not meet the need of pioneer development. On the other hand, three-dimensional integrated circuits (3-D ICs) become more and more popular to satisfy the multi-function chip development. One of the best solutions of these needs is the ultra-fine pitch micro-bumps. The micro-bumps can...
In this decade, the Moore's law does not fit the trend of technological improvement any more. In order to keep the increasing rate of device density and I/O numbers, the size of devices shrink rapidly. In this kind of condition, the stack of integrated circuit (IC), which is also called three-dimensional integrated circuits (3-D ICs), is a preferable solution of the next-generation products. There...
Recently, the dimensions of the flip-chip solder bumps reduce to about 20-30 micrometers, also known as "micro-bumps" sandwitched between two Si chips. In such a structure, electromigration and thermomigration behaviors in the micro-bumps are not clear now. In this study, the temperature map distribution of Al traces and Al pads in CoC and C4 structures during current stressing was directly...
The ultra fine pitch micro bump became the future trend due to the development of 3D IC. In this research, three-dimensional simulation was employed to examine the temperature distribution in micro SnAg solder bumps. According to the result, the temperature distribution in solder bump of micro bump is nearly uniform. In addition, the hot side is near the substrate side, whereas the cold side is near...
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