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This article consists of a collection of slides from the authors' conference presentation. Some of the topics discussed include: Introduction and Background; NARA Architecture; NARA Key Features and Functions; NARA Chip Implementation; Target Applications; Conclusion.
This paper proposes the world's first single-chip 4K 60fps 4:2:2 HEVC video encoder LSI (named “NARA”) with 8K scalability for broadcasting with professional high image quality. It consists of a prediction core with a new prediction mode decision framework, dual coding cores, controlling RISCs, and high speed data buses with multichip 8K configuration, using 28nm CMOS technology. The NARA LSI will...
We propose a novel energy-efficient power saving technique coordinating CPEs via ONU. In addition, we first evaluate the proposal in a 10G-EPON system whose ONU sleep mechanism complies with IEEE Std. 1904.1 SIEPON and IEEE 802.3az EEE. It is revealed that the proposal yields ONU power savings of the order of 42 %. Moreover, it reduces the excessive latency by 40 % compared to unsynchronized power...
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