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This paper presents a low-power adaptive edge decision feedback equalizer (DFE) for 10 giga-bits-per-second (Gbps) serial links with 4 PAM (pulse-amplitude-modulation) signaling. Optimal tap coefficients are obtained adaptively using a sign-sign least-mean-square (SS-LMS) algorithm that minimizes the jitter of equalized data. Low-voltage-differential-signaling (LVDS) tap generators that double DFE...
This paper presents a comparable study of the locking characteristics of phase-locked loops (PLLs) with an integrating bang-bang phase detector with that of PLLs with an Alexander full-rate bang-bang phase detector. Both periodic and single-event data transients are used to investigate the lock performance of two PLLs with identical configuration and components but different phase detectors. Simulation...
This paper presents a new time integrator for mixed-mode signal processing. The proposed time integrator consists of two time adders realized using a time-to-voltage and voltage-to-time conversion mechanism. All transistors of the proposed time integrator operate in an on/off mode, the time integrator is fully compatible with digital-oriented CMOS. The effect of nonidealities including charge injection,...
This paper presents an adaptive Decision-Feedback Equalizer ADFE utilizing a proposed hexagon eye-opening monitor for multi Gbps serial links. The adaptation process of proposed ADFE depends on the error signals which are delivered from error detection unit EDU. The EDU employs a hexagon eye-opening monitor H-EOM to detect the violations of the received data signals after the comparison with three...
This paper proposes a charge-domain quadrature down-conversion sampling mixer with improved filter functionality. An 4-path bandpass filter and a quadrature sampling mixer are integrated in a cascode architecture to minimize power consumption while providing a degree of programmability. The proposed design is applicable to heterodyne receivers for suppressing aliasing signals, large out-of-band blockers,...
RFID technology has been widely used in logistic, automation and authentication applications, but it still has many potential issues such as the risks of privacy and security. This paper presents a novel RFID security protocol based on XTEA algorithm. Analysis of the security and privacy of this novel protocol is performed using FPGA based prototyping platform. Different attack models are implemented,...
This paper provides an overview and in-depth examination of the state-of-the-art of remote frequency calibration of the system clock of passive wireless microsystems. Frequency calibration using the carrier and the envelope of received RF signals, frequency calibration using injection-locked division, carrier injection-locking, digital trimming, envelope injection-locking with integrating feedback...
Intersignal timing skew gives rise to reduced timing margins at receivers and limits the data rate of parallel links. This paper proposes a new intersignal timing-skew-compensation technique for parallel links with voltage-mode incremental signaling. The proposed technique employs an early/late block to detect the rising and falling edges of the pulses generated by intersignal timing skews at the...
This paper proposes a new current-integrating bang-bang phase detector that is insensitive to data transient disturbances. The phase detector extracts early-late phase information between the input and retimed data by integrating the input data and its complementary on two identical capacitors. In addition, it employs only one regenerative DFF for phase detection, significantly lowering hardware cost...
This paper proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signaling. The proposed current-mode receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values for convenient phase comparison. The feedback at the front-end of the receiver minimizes the dependence...
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