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This paper presents a dual-band 2×2 WiFi transceiver in 28nm bulk CMOS. Achieved receiver and transmitter EVM floor at 5GHz for 160MHz per channel are −35dB and −33dB, respectively. The 2.4GHz integrated PA provides 26.5dBm saturated output power while its 5GHz counterpart delivers 26dBm. The 2.4GHz receiver features mixer first architecture while the transmitter includes a 2nd harmonic notch for...
A K-band PA using adaptive-bias technique is developed in 0.18µm CMOS technology. By means of controlling the proposed FET-type variable resistor, the proposed adaptive-bias circuit can dynamically adjust the gate bias of the PA according to the input signal with low insertion loss at K-band. This PA has a peak PAE of 14.9% while the output power is 15.8 dBm at 24 GHz, and the P1dB is 13.9 dBm with...
This paper proposes a new pre-distortion linearizer for CMOS power amplifier (PA) to improve the performance of the output 1-dB compression power and power added efficiency at 1-dB compression power. By adopting the proposed pre-distortion linearizer, a 60 GHz cascode PA with 13.7-dBm 1-dB compression power (P1dB) and 14.3% power added efficiency (PAE) at P1dB is demonstrated. The chip size is 0.55...
A fully integrated K-band power amplifier is designed and fabricated in 0.18-µm CMOS technology in this paper. The conventional cascode power amplifier benefits from high gain and output power, but the efficiency is not well discussed before. In this study, the voltage variation and the large-signal performance of cascode PA are analyzed, and the new design strategy for the optimal bias selection...
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