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The susceptibility of memory elements (latches, flip-flops) to soft errors is increased as CMOS technology scales down, due to multi-node charge collection by the impact of energetic particles on silicon. Existing design solutions provide partial or no immunity to SEUs that affect a pair of nodes. In this work, we propose a new latch topology, which provides complete protection from SEU related double...
Single event upsets (SEUs) that affect adjacent nodes in a design, by charge sharing mechanisms among these nodes, are a great concern in nanometer SRAMs, since pairs of cells are influenced. The concern is also extended to SEU related soft error tolerant latch designs, where multiple memory elements are exploited. In this work, we deal with double node charge sharing SEUs (DNCS-SEUs) that affect...
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