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Serious tungsten corrosion after tungsten chemical mechanical planarization (W CMP) is found to correlate to the high via resistance. According to via design layout analysis, the W plug recess is strongly dependent on the underlying metal line area and via hole size. The via W plug recess becomes worse as via size shrinkage and underlying metal line area increasing. The low corrosion W polishing slurry,...
Most of simulation activities implemented on semiconductor manufacturing are focus on the device characteristics, and electrical properties. Less investigation pays attention on micro-structure stress/strain calculation with finite element analysis. This investigation demonstrates the ANSYS simulation results match with real cases results. The chip-level micro-structure simulations include the metal...
Integrated circuit (IC) chip fabrication consists of hundreds of complicated and time-consuming processing steps like wafer processing, testing and packaging. However, it is hard to achieve the efficiency and output while maintaining the high product quality and reducing overall costs simultaneously in the complexity of semiconductor manufacturing. In order to achieve the low cost manufacturing via...
Current 2D planar NAND has its limitation for expanding capacity due to the performance and reliability intrinsic characterization will be impacted as device scaling below the 20nm technology node. Such as write bits error, data retention and read disturb, etc. Continued scaling increases the effect of cell-to-cell interference, which widens the program state width. 3D vertical stacking memory cells...
Chemical-mechanical polishing (CMP) technique is widely applied in the semiconductor industry nowadays. The CMP working mechanism is the interaction of the chemical reaction and mechanical polishing to remove the undesired materials in the circumstance with the feeding slurry and the polishing pad. As the device scale shrink, defect and uniformity control have become the major challenge and critical...
Chemical Mechanical Planarization (CMP) become a mainstream process in semiconductor industry, it is a key technology to generate flat and smooth surface at several critical steps in the manufacturing processes. The planarization performance is influenced by topography characteristics, line/space width, pattern density, slurry chemistry, rotation speed, PAD type, force/pressure, etc. However, as device...
Micro-crack of ILD oxide in peripheral area leads to wafer sort leakage failure issue. However, high nuisance rate in peripheral area inspection cannot monitor it effectively. This paper addresses a new methodology to improve the inspection sensitivity by transferring the wafer sort specific failure sites into GDS coordinates on design layout. These failure sites are the patterns of interest (POIs)...
Thickness variations of ILD CMP induced yield loss at wafer edge is simulated by 3D Sentaurus Interconnect, in order to achieve more authentic condition, we adopt the image contour extraction technique to stream the genuine contact contour gds together with STI, POLY, ML database. The results demonstrates that when the thickness is over 7k at wafer edge, there is no electric current found, and it...
An optimization of e beam inspection (EBI) new methodology is implemented to monitor the defective issues in semiconductor manufacturing. The benefits of optimized e beam inspection methodology not only can switch the care area among the inspection tools, but also minimize the inspection shots and the time consumption in EBI application. Inspect tiny physical defects with high throughput using EBI...
FOUP mini-environment in-line contaminants analysis is introduced into 55nm technology node product. It demonstrates that the inorganic ions /VOC contaminants of some processes cannot be resolved by FOUP N2 purge action only, special taking good care for critical layers to prevent the irretrievable yield loss is necessary. The performance of FOUP N2 purge at different kinds of module processes are...
Color abnormal phenomenon in post Cu chemical mechanical planarization (CMP) is found in 3X nm flash memory. TEM cross-section shows that there is no Cu residue but has localized thickness variation. This color abnormal phenomenon cannot be eliminated with subsequently Cu and barrier polishing. According to experimental results, the non-uniform inhibitor distribution of Cu slurry issue will enhance...
Generally CD (critical dimension) measurement is an important role for verify the FEM (Focus Exposure Matrix) process window. However, the generally CD measurement is rough due to only measure few site in wafer. The results cannot get the high accuracy information for verification the FEM process window and waste a lot of FEM process time. In this paper, we have demonstrate a new methodology that...
The goal of this research is to improve bending issue and etch durability of amorphous carbon hard mask film (APF). The design of experiments (DoE) employed variable conditions of the spacing, RF power, precursors flow (C3H6 or C2H2) and temperature. High Young's modulus and high sp3/sp2 bonding ratio can increase the etching resistance, and strengthen the high aspect ratio patterning structures.
Yield impacting systematic defects finding is no longer just relied on Design Rule Checking (DRC) provided by designer or Lithography Rule Checking (LRC) provided by post-optical proximity correction (OPC) results. An inspection flow is proposed in this paper, which is combining the inspection KLA tool and Hotspot Pattern Analyzer (HPA) database software to do the systematic defects filtering, sorting,...
Airborne molecular contamination (AMC) becomes more serious in Fab as the device shrinks and wafer size increases, an economic way for preventing these contaminations is to use N2 purge charging process. The practical FOUP N2 purge engineering is addressed here, which includes the maintenance and management of FOUPs, N2 purge charging flow rate, the design of nozzle, selection of nuzzle material,...
The different inspection methodologies in e beam are put together to compare their inspection performance on irregularly periphery via plugs. The results demonstrate hot spot inspection mode has better alignment performance and higher sensitivity than leap and scan mode. Hot spot mode can inspect the tiny variation of voltage contrast (VC) with high sensitivities. One type of VC variation inspected...
In this paper we studied capturing buried void defects in copper (Cu) wires using an electron beam inspection (EBI) system. These are defects of interest (DOI) to integrated circuit (IC) manufacturers because typical defect inspection techniques cannot capture them: optical defect inspection, EBI voltage contrast (VC) mode, and EBI physical detection mode. We used an engineering system to study a...
Advanced bright field (BF) inspector have many functions to increase the defect signal, and suppress the background noise. However, it will take much time to fine tune an optimized BF inspection recipe. The aim of this paper is to propose a faster way to select the optimized optics.
The effects on the mini-environment of FOUP (Front Opening Unified Pod) by N2 purge are evaluated with various processes. From the experimental results, it is effective to suppress the formation of condense defect, corrosion defect and extend the queue time at critical process steps.
Advanced high performance dark field (DF) inspection is usually utilized at larger defects and the excursions in etch, chemical mechanical polish (CMP) or film deposition processes inspection at high production throughputs. Here demonstrates risky scratch defects right after post poly-silicon CMP captured by DF inspection technique.
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