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This paper presents a performance-optimized version of the flexible triangle (FTS) block-matching search algorithm. The FTS is a fast block-matching algorithm for motion estimation proposed in previous work that, given a block of pixels, is used to search for the best-matching block in a given search area using only a selected subset of available positions rather than searching all available positions...
This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms...
One of the challenging problems in Networks-on-Chip (NoC) design is optimizing the architectural structure of the on-chip network in order to maximize the network performance while minimizing corresponding costs. In this paper, a methodology for multi-objective optimization of NoC standard architectures using Genetic Algorithms is presented. The methodology considers two cost metrics, power and area,...
Networks-on-Chip (NoC) architecture design faces a trade-off between different conflicting metrics. In this paper, we target one aspect of this trade-off: area versus average delay. The NoC architecture generation is formulated as a two-objective optimization problem and a Genetic Algorithm (GA)-based technique is used to solve it. According to the application requirements and the design constraints,...
In this paper, we present a novel approach in Networks-on-Chip topology optimization, by considering the network power consumption, packet transmission delay, and system reliability, simultaneously. We use the Particle Swarm Optimization technique to acquire the most suitable topology architecture, which achieves maximum reliability as well as minimum delay and power consumption. The optimization...
Network delay is a major design parameter for Networks-on-Chip (NoC)-based applications. Improving NoC delay could be achieved at different design phases. At the system level, we study in this paper the impact of the network topology on NoC system delay using graph-theoretic concepts. A topology-based model is developed to calculate the average NoC delay, which is caused by links and routers. The...
Networks-on-Chip (NoC) architecture design faces a trade-off between cost and performance. In this paper, we target one aspect of this trade-off: area versus average delay. The NoC architecture generation is formulated as a two-objective optimization problem and a Genetic Algorithm (GA)-based technique is used to solve it. According to the application requirements and the design constraints, the optimization...
We present a new analytical model of MAC layer for wireless ad hoc networks that takes into account channel bit errors and frame retry limits for a two-way handshaking mechanism. This model offers flexibility to address key design issues such as the effects of traffic parameters and possible improvements for wireless ad hoc networks. We illustrate that an important parameter affecting the performance...
In wireless multihop ad hoc networks, the use of the RTS/CTS mechanism does not completely eliminate the hidden-terminal problem. Considering the hidden-terminal problem adds complexity to the existing analysis for single-hop networks. In this paper, we provide precise and accurate analytical models for quantifying the throughput and delay in wireless multihop ad hoc networks. The proposed analysis...
In this paper, we present a simple and realistic two-class QoS model for random access systems. This model provides a general and effective approach to QoS classification by categorizing the available resources into distinct service classes. We present a simple Markov model of the subscriber stations to define the system transitions and state probabilities. Performance metrics based on random access...
This paper presents a new processor array architecture for scalable radix2 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architecture extracted by C. Koc, and also the multiplier bits are fed serially to the first processing element...
One of the challenging problems in application-specific networks-on-chip (ASNoC) design is customizing the topological structure of the on-chip network in order to meet the application requirements with the minimum possible cost. In this paper, the area cost of ASNoCs is reduced by using network partitioning techniques. Given the application core graph, the partitioning problem is formulated as an...
We present a new analytical model of MAC layer for wireless ad hoc networks that takes into account frame retry limits for four-way handshaking mechanism. This model offers flexibility to address key design issues such as the effects of traffic parameters and possible improvements for wireless ad hoc networks. It effectively captures the important network performance characteristics such as throughput,...
The medium access control frame duration is limited in wireless local area networks. Severalmodels have been applied to get better utilization of this frame. The frame is composed of different phases and adjusting the use of one phasemay effect the other phases' durations. WiMAX and IEEE802.11 standards have similar physical layer. Channel error due to noise or fading is another problem encounters...
In this paper, we present a simple two-class QoS model for random access systems. We provide a practical mechanism for categorizing the available resources into two distinct service classes prior to medium access. We use an a Markov chain model to define the states and transitions, and derive the system access success probability. This provides a mathematical basis for an accurate model that can be...
A datacube model for atmospheric pollutants is presented in this work. The value of interest is flux of pollutant deposition versus several attributes such as pollutant type, location, geographic scale, etc. We present also an analytical model for the effect of wind gusts on the pollutant distribution. The model takes into account random variations in wind speed and instrumentation noise. We consider...
Networks-on-Chip (NoC) topology generation faces a trade-off between cost and performance. In this paper, we evaluate different custom and standard NoC topology generation techniques with respect to area and delay. The area needed for the topologies generated by these techniques is evaluated according to their routers area and number of global links. The delay is compared in terms of average internode...
In this paper, we applied an error control protocol for wireless local area network in medium access control. Hiperlan\2 random access phase is taken as an example. We applied quality of service support in the random access phase. Analytical model is developed for the backoff strategy with error control protocol. The performance metrics are shown.
In this paper, we study the impact of random access phase in Hiperlan\2 medium access control frame. We propose and study several backoff strategies for the unsuccessful users in the random access phase. Markov chain modeling is used to model the random access channels. We also applied the error control to the transmission state. Instead of assuming the channel is error free, we studied the impact...
The choice of a network topology for a networks- on-chip based application significantly impacts its power consumption. In this paper, we propose a new methodology to reduce the total power consumption of the global router-to-router links by selecting the optimal network topology. The proposed methodology merges three mapping approaches: network partitioning, standard topology mapping, and long-range...
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