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A clock generator using an injection-locked oscillator (ILO) offers remarkable jitter performance with low-overhead of additional circuits such as injection switches. Because the injection clock cleans the edge of the oscillator in every injection period, jitter accumulation is avoided. However, the ILO alone causes a severe reference spur owing to the mismatch between the desired oscillation frequency...
A 180° phase-shift digital delay-locked loop (DLL) for LPDDR4 memory controllers is composed of a global DLL and a local DLL for each channel. The global DLL uses a time-to-digital converter to achieve fast-locking, and then shuts down to reduce power consumption. The local DLL, locking based on delay codes from the global DLL, uses a digital window phase detector (PD) and tracks the input clock phase...
This paper describes a CMOS interface circuit for silicon photonics. 20-Gb/s operation of an optical receiver front-end circuit is demonstrated using an optical signal applied to the optical front-end. The transimpedance amplifier (TIA) is based on an inverter with resistive and inductive feedback for low power consumption and frequency compensation. A negative capacitance generation is employed in...
This paper describes the design and performance of a 10-Gb/s optical receiver front-end fabricated in a 0.13-μm CMOS technology. To realize a wide bandwidth transimpedance amplifier (TIA) that has large input parasitic capacitance, an area-efficient stacked spiral transformer is implemented. By using a capacitance multiplication technique, the baseline wander resulting from a current offset...
This paper presents an IEEE 1588-2008 adapter that provides existing Gigabit Ethernet equipment with the functionalities required to clock synchronization on the order of sub-microsecond. To compensate the time error caused by the queuing delays in the Gigabit Ethernet equipment, the adapter measures the residence time and runs the peer delay mechanism for the equipment. Major functional blocks including...
A fully integrated 40-Gb/s transceiver is implemented in a 0.13-mum CMOS technology. This paper describes the challenges in designing a 20-GHz input sampler, a 20-GHz quadrature LC-VCO, a 20-GHz bang-bang phase detector, and a 40-Gb/s equalizer. The transceiver occupies 1.7 times 2.9 mm2 and dissipates 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 215-1 PRBS...
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