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In this study, we propose a new technology to fabricate pseudo tri-gate vertical (PTGV) MOSFETs without p-n junctions, named junctionless PTGVMOS (JPTGV). According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60mV/dec, Ion/Ioff ~ 1010, and low interface trap density are all achieved. The device without p-n junctions provides an easier way for...
A new planar-type body-connected FinFET structure produced by the isolation-last self-align process is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. The new process step first defines the gate region and then the active region, thus it can achieve fully self-alignment undoubtedly. Besides, due to the isolation-last process (ILP), an additional body region (ABR)...
In this study, we propose a novel polysilicon thin-film transistor with multi-trenched body (MTB TFT). According to the ISE-TCAD simulations, our proposed MTB TFT gets a steep subthreshold swing (S.S.), a reduced drain-induced barrier lowering (DIBL), a lower drain off-state leakage, and a higher ION/IOFF ration, in comparison with a conventional poly-Si TFT. In addition, due to the MTB scheme, the...
This paper examines the effect of block oxide height (HBO) on a self-aligned (SA) source/drain-tied n-shaped block oxide field-effect transistor (S/D-tied nBOFET). According to the simulation results of a two-dimensional (2-D) numerical simulator DESSIS, the height of the block oxide is one of the important parameters for the suppression of short-channel effects (SCEs). Hence, the forming of HBO becomes...
A novel device architecture-the self-aligned pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) FET-is presented for the first time in the field of silicon-on-insulator (SOI) technology; this new device demonstrates how to decrease the self-heating effects in the SOI-based devices. Two-dimensional simulations show that the cost of building an S/D tie into the UTSOI-FET is a modest...
In this work, a novel fully depleted silicon-on- insulator MOSFET with block oxide (bFDSOI) is proposed to investigate the influence of Si-body thickness on the characteristics of the device. Based on the two-dimensional (2-D) simulation results, the proposed structure exhibits better ultra-short-channel behavior such as reduced drain-induced barrier lowering (DIBL) and better subthreshold swing when...
In this paper, we propose a novel fully depleted silicon-on-insulator MOSFET with block oxide enclosed body (bFDSOI). To differ with the conventional FDSOI MOSFET, the proposed SOI structure shows enhanced performance by exploiting sidewall spacer process. For this new bFDSOI device, the electric field between the body and the source/drain (S/D) region is restrained by the block oxide resulting in...
In this paper, a vertical n-channel enhancement-type MOSFET with internal block layer (bVMOS) is investigated theoretically. In the proposed structure, the internal block layer comprises a buried block layer and a sidewall block layer. We also test three blocking materials (ex. doped Si, nitride and oxide) for performance comparisons. That is, the p-n junction region between the substrate and drain...
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