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In this paper a specific implementation of the transceiver controller is presented, based on a high speed serial interface (HSSI) protocol-JESD204B. The implementation of this protocol provides less pin counts, lower complexity and more accurate timing control than the traditional parallel data transportation from ADC to DAC. This paper gives a design of the transceiver controller and the verification...
A half-rate clock and data recovery (CDR) circuit for 60GHz communication with 20Gbps QPSK modulation in 65nm CMOS is presented. A hybrid DC-offset cancellation loop (DCOC) is proposed to calibrate the input offset. A duty cycle distortion (DCD) cleaning up circuit is adopted to minimize the negative impact on the half rate sampling in the CML-CMOS conversion, and a quadrature clock calibration (QCC)...
This paper presents a source synchronous receiver data lane design in 65nm CMOS process. The data lane circuit consists of a pre-amplifier which can compensate over 8dB channel loss and a half-rate digital CDR based on phase-interpolator. The CDR bandwidth is programmable by using a digital FIR filter. This design uses variable offset amplifier technology to increase sensitivity of the receiver. And...
In this paper, a novel clock and data recovery scheme for 10Gbps source synchronous receiver is presented in 65nm CMOS technology, which includes the implementation of a quadrature clock generation circuit and a 10Gbps CDR circuit. The quadrature clock generation circuit is based on an open loop delay line, avoiding the design of the complex DLL or PLL loop which is often used in source synchronous...
In this paper, a baseband transceiver is proposed for IEEE 802.15.4 and for one 2.4G RFID protocol. This transceiver supports OQPSK with direct sequence spread spectrum (DSSS), MSK without spread spectrum, and DBPSK with DSSS. In this design, those three demodulations share most of their hardware blocks to reduce area and power consumption. This baseband transceiver is part of a multi-mode and multi-band...
In this paper, a 10Gbps PI-based CDR circuit is presented in 65nm CMOS technology. The circuit is composed of a phase selector, a phase interpolator, a sample unit, a synchronize unit, a phase detector, and CDR logic. Half-rate clock is adopted to lessen the problems caused by high speed clocks and reduce power. The simulated worst phase step of phase interpolator is 26.7% larger than the average...
This paper proposes a theoretic error analysis framework as well as corresponding calibration methods for a mobile 3D data acquisition system equipped with LiDAR and GPS/IMU. Our framework considers inherent errors of variable sensors, installation errors, and time synchronization errors among different sensors. Our framework is enhanced by an empirical error analysis method based on a triangulated...
Ultra-wideband (UWB) technology has received great attention in recent short-range communication systems and been considered one of the potential candidates for upcoming IEEE 802.15.6 body area network (BAN) standard. High penetration capability and high precision ranging with a wide bandwidth of up to 7.5GHz (from 3.1GHz to 10.6GHz) make it easy to image the organs of human body for biomedical applications...
Low power consumption and efficient power supply are very crucial for biomedical implant electronics. The power issues in the design of implanted devices are addressed and three distinct design cases, including a low power stimulator chip for retinal prosthesis, a novel cochlear implant system with multi-level power optimization and a wireless monitoring system of total knee replacement, are demonstrated...
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