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A 10–60 Gb/s wireline transmitter with a 4-tap multiple-multiplexer (MUX) based feed-forward equalization (FFE) is presented. It adopted a novel 4:1 MUX to increase the bandwidth of the final seiralizing stage. Simulation result shows that the proposed 4:1 MUX operates over a wide range of data rate between 10 and 60 Gb/s. Designed in 65 nm CMOS technology, the transmitter exhibits a low jitter of...
This paper presents a 40–80 Gb/s quarter rate PAM4 wireline transmitter. The transmitter incorporates a 2-tap feed-forward equalizer (FFE) based on multiple-multiplex (MUX) and a parallel PRBS7 generator. The transmitter is achieved in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed transmitter can work at 40–80 Gb/s with 4-level pulse amplitude modulation...
A serial-link repeater chip with a single stage continuous-time linear equalizer (CTLE) and a 3-tap feedforward equalizer (FFE) is realized in a 0.13μm SiGe BiCMOS technology. The CTLE with the negative capacitance circuits is implemented to achieve a larger high-frequency boosting at the receiver side. By utilizing the LC-based delay elements, the FFE accomplishes the transmitter de-emphasis without...
This paper introduces a fully-integrated wireline transmitter operating at 40Gb/s. The transmitter incorporates a combiner of 64:1 MUX and 2-tap Feed-Forward-Equalizer (FFE). The transmitter is achieved in 65nm CMOS technology. The simulation results show that the proposed transmitter can work at 40Gb/s with a −11dB RLGC channel. The simulation power consumption is 76 mW under 1.08V supply, and the...
This paper introduces a fully-integrated wireline transmitter operating at 28Gb/s. The transmitter incorporates a 3-tap Feed-Forward-Equalizer (FFE) with Flipflop-based delay to equalize the channel. T-coil networks are used with ESD protection circuits at transmitter's output to realize impedance matching and bandwidth enhancement. The transmitter is fabricated in 65nm CMOS technology. The measurement...
This paper presents a 40Gbps SerDes transceiver consuming only 190mW power. The transmitter employs serializing time window search technique and 2-tap pre-emphasis. The receiver implements power-efficient front-end circuits including current-integrating FFE and cascaded dynamic comparators. The CDR employs a bang-bang phase detector, and the integral path and proportional path are separated. Fabricated...
A 4×20-Gb/s source-series-terminate (SST) transmitter with 2-tap FFE and far-end crosstalk (FEXT) cancellation is presented. The FFE and crosstalk canceller (XTC) are merged together with the SST driver. The proposed transmitter architecture with divider-less clock generation can not only guarantee the timing requirement for the highest-speed serialization under PVT variation, but also save a lot...
This paper presents a 40 Gb/s (38.4-to-46.4 Gb/s) half rate SerDes transmitter with automatic serializing time window search and 2-tap pre-emphasis. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at the highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. A divider-less sub-harmonically...
This paper describes the co-design of equalizers for 40Gb/s transceiver. A feed forward equalizer (FFE) is applied to the transmitter, while an adaptive continuous time linear equalizer (CTLE) is applied to the receiver. The innovation is that both equalizers cooperate with each other to equalize the channel, and T-coil networks are used with ESD protection circuits in both transmitter's output and...
This paper describes the design of a source-synchronous transmitter in 65nm CMOS technology. The transmitter consists of five data lanes plus one forwarded clock lane. Every single lane works at 10Gb/s. The clock distribution path is carefully designed to ensure the synchronous of the divided clock in every data lane. And this design is power efficient by optimizing the structure of MUX. Furthermore,...
This paper presents a data lane circuit for transmitter of 4.8Gbps serdes in 65nm CMOS process. The data lane circuit mainly consists of 32∶1 multiplexer (MUX) and equalizer. MUX adopts half-rate architecture and CMOS circuits to relax clock requirement and save power. The equalizer is a 4-tap feed forward equalizer (FFE) that can operate at two driving modes. Measurement shows that FFE can compensate...
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