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This paper presents an improved digital tanlock loop architecture that has linear phase detector characteristics. These characteristics were linearized by removing the fixed time delay unit in the original time delay tanlock loop (TDTL) and using a modified DCO (digital controlled oscillator). The modified DCO incorporates lookup tables to generate two outputs with quadrature relationship. The two...
A dual Time Delay Digital Tanlock Loop (D-TDTL) topology is proposed in this work. The system consists of a stacked dual loop of which the top one acts as a Frequency Lock loop (FLL) for the bottom loop, while the latter is a phase lock loop (PLL) that enhances the overall phase of the system. The main advantage of the proposed system is the large reduction of phase noise or jitter which makes it...
This paper presents the architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage utility grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock loop (PLL) to synchronize a PV generator...
A new technique for fast error correction of the TDTL (time delay digital tanlock loop) is proposed. The technique is based on early comparison of the input signal frequency with that of the loop filter output. The result of this comparison is then used to select an optimum value for the loop filter output. This technique eliminates the need for continuously changing the loop filter coefficient. The...
A circuit topology for an AC-DC single-phase single-stage half-controlled converter with reduced line current harmonics is presented. It is shown that these harmonics are reduced below limits imposed by relevant international standards governing the generation and injection of harmonics into the distribution systems by equipment which draws current less than 16 A. The paper also demonstrates the use...
This paper presents a second order time delay digital tanlock loop with improved locking as well as acquisition performance. The former is achieved through replacement of the delay unit of the TDTL by a variable one whose phase error is controlled by the output of the phase detector. This approach maintains the quadrature relationship between the two TDTL channels and hence results in a linearized...
A microcontroller-based circuit topology for a single-stage single-phase AC-DC converter with line current harmonics minimisation properties is presented. The circuit is based on the half-controlled AC-DC converter circuit in which the active devices are two power MOSFET transistors. The switching action of the transistors controls the shape and hence the harmonic content of the supply current to...
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