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The complexity of verifying a System on Chip (SoC) increases dramatically due to the integration of heterogeneous components and complicated interactions among components. Despite the functional features and corner cases of a component could be exercised thoroughly during block-level verification, it is important to re-certify the component after integrating into an SoC. In this paper, we propose...
Design fingerprinting is a means to trace the illegally redistributed intellectual property (IP) by creating a unique IP instance with a different signature for each user. Existing fingerprinting techniques for hardware IP protection focus on lowering the design effort to create a large number of different IP instances without paying much attention on the ease of fingerprint detection upon IP integration...
A triband 65nm CMOS tuner is designed and implemented for first ATSC mobile DTV SoC. It supports VHF-I, VHF-III, and UHF bands. The tuner achieves a 2.5/3.0/4.0dB NF at VHF-I, VHF-III and UHF band respectively, while consuming less than 100mW. By using narrowband LNA architecture with input and load tuning ability, it can meet linearity requirement for ATSC mobile with small power consumption. It...
A multi-standard multi-band tuner for mobile TV SoC satisfying the GSM850 & GSM900 Interoperability (IOP) is presented. The single-chip SoC satisfies all requirements of DVB-H/T, ISDB-T, and DAB application with margin. Moreover, this SoC meets not only the GSM900 IOP which is described in MBRAI 2.0, but also GSM850 IOP, in DVB-T/H mode. To suppress GSM transmitter signal in UHF band, LC-tuned...
A multistandard, multiband mobile TV SoC that integrates RF tuner, demodulator, FEC, hardwired MPE-FEC, ARM CPU and SRAM is presented. The RF tuner supports direct and low IF conversion to optimize power consumption and performance of each standard. Implemented in 65 nm CMOS, it occupies 23.2 mm2. For DVB-H/ISDB-T 1-segmentation/TDMB, the total SoC power consumption is 203/101/143 mW.
Most VLSI watermarking techniques do not allow different authorships of multiple Intellectual Property (IP) cores to be detected directly in the field after the IPs have been integrated, fabricated and packaged into chip. Watermark inserted at the design-for-testability (DfT) stage makes its direct detection after chip packaging possible, but it protects only the downstream placement-and-routing design,...
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