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We present a new critical net reshape-router for high-performance VLSI layout design. Our router firstly rips up a critical-net and calculates its approximate RMST (Rectilinear Minimum Steiner Tree) and puts the restricted area for reshape routing. Secondly a multi-layer maze router searches the path of the net inside the restricted area. Our router can search the approximate optimal shape of RMST...
In this paper, we propose a basic crosstalk avoidance router using two area usage restrictions. They are “a wide pitch restriction” and “a bounded area restriction”. The wide pitch restriction means that the router using only wider pitch than the minimum pitch from the process technology rule. The bounded area restriction means that a router only executed inside minimum bounding box with some redundancy...
With the increasing risk of IP reuse in System on Chip (SoC) design, intellectual property (IP) techniques becomes one of the most important issues. Compare with watermarking, fingerprinting is a more effective method because is not only protects the IP owner's benefits but also user's rights. In this paper, we firstly propose a multilevel fingerprinting method for IP protection. In the typical field...
In this paper, we propose a new ideas of the Simulated Annealing method to improve the execution time. SA method is an effective optimization algorithm for combinatorial problems such as a placement design for VLSI Chip, but a deficiency is the long execution time. Therefore, to improve the execution time of SA algorithm is widespread concern. In this paper, we propose a new idea TOSA that traces...
With the increasing complexity of integrated circuits, system-on-chip (SoC) design is proved an effective design method due to intellectual property (IP) reuse. To protect IPs from piracy, watermarking techniques have significantly advanced as an IP protection (IPP) technique. It is an important work to judge the watermarking solutions achieve the goals or not. In this paper, we analyze several representative...
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