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This paper discusses a low-power test scheme compatible with both test compression and built-in self-test environments. The key contribution is a detailed analysis showing that a simple power-aware controller may allow significant reductions of toggling rates when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications...
We propose a yield improvement methodology which repairs a faulty chip due to the logic defect by using a repairable scan flip-flop (R-SFF). Our methodology greatly improves an area penalty, which is a large issue for the logic repair technology in the actual products, by using a repair grouping and a redundant cell insertion algorithm, and by pushing the design rule for the repairable area of R-SFF...
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