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We propose a yield improvement methodology which repairs a faulty chip due to the logic defect by using a repairable scan flip-flop (R-SFF). Our methodology greatly improves an area penalty, which is a large issue for the logic repair technology in the actual products, by using a repair grouping and a redundant cell insertion algorithm, and by pushing the design rule for the repairable area of R-SFF...
In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve...
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