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Pentacene organic thin-film transistor (OTFT) using Pd as gate electrode is proposed, with high-k LaZrO as gate dielectric. The Pd film is prepared by e-beam evaporation and then the LaZrO film is deposited by reactive sputtering in Ar/O2 ambience followed by an annealing in N2 at 400 °C. The OTFT achieves an obvious increase in carrier mobility (to 1.02 cm2/V·s), as compared with its counterpart...
Pentacene organic thin-film transistor (OTFT) with high-κ HfTiO gate dielectric has been fabricated. The effects of fluorine plasma and ammonia annealing on the properties of the OTFT have been studied. After treating the dielectric in the plasma, the carrier mobility of the transistor can be improved by about 5 times to 0.0883 cm2/V·s. Moreover, the fluorine plasma treatment can shift the threshold...
OTFTs with P3HT as organic semiconductor and HfTiO as gate dielectric have been studied in this work. The HfTiO dielectric film was prepared by RF sputtering of Hf and DC sputtering of Ti at room temperature. Subsequently, the dielectric film was annealed in an NH3 or N2 ambient at 200??C. Then a layer of OTS was deposited by spin-coating method to improve the surface characteristics of the gate dielectric...
HfTiON gate dielectric is fabricated by reactive co-sputtering method followed by annealing in N2 ambient. The effects of Ti content and annealing temperature on the performances of HfTiON gate-dielectric Si MOS devices are investigated. Experimental results indicate that gate capacitance is increased with increasing Ti content. However, when the Ti/Hf ratio exceeds ~1.75, increase of the gate capacitance...
In this work, Al/HfTiON/n-Si capacitors with different sputtering and annealing temperatures are studied. Larger accumulation capacitance and flat-band voltage are observed for samples with higher sputtering or post-deposition annealing temperature. Gate conduction mechanisms are only affected by sputtering temperature slightly. The flat-band voltage shift and interface-state density at midgap under...
In this work, Ge MOS capacitors with Y2O3 gate dielectric were fabricated. The effects of annealing in N2, NH3 O2 or NO ambient were investigated. Experimental results demonstrated that the NO annealing could improve both electrical properties and reliability of Ge MOS devices with Y2O3 dielectric. On the other hand, the NH3 annealing resulted in H-related traps while the O2 annealing suffered from...
A hydrogen sensor based on InGaN/GaN multiple quantum wells (MQWs) was fabricated. A gate dielectric HfTiO was added to stabilize its performance at high temperature. Its hydrogen-sensing properties were studied at high temperatures from 100??C to 500??C. The sensor showed promising hydrogen-sensing properties over a wide temperature range, and could still function beyond 500??C.
Thin LaTiON gate dielectric is deposited on Ge (100) substrate by reactive co-sputtering of La2O3 and Ti targets under different Ar/N2 ratios of 24/3, 24/6, 24/12, and 24/18, and their electrical properties are investigated and compared. Results show that the LaTiON gate-dielectric Ge MOS capacitor prepared at an Ar/N2 ratio of 24/6 exhibits highest relative permittivity, smallest capacitance equivalent...
In this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interlayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interlayer...
Si MOS capacitors with HfTa oxide and oxynitride as gate dielectric were fabricated. Moreover, AlOxNy or TaOxNy was used as the interlayer between HfTa oxynitride and Si substrate to improve the electrical quality of the capacitors. Experimental results showed that the HfTaOxNy capacitor with TaOxNy interlayer achieved better performance with larger capacitance and smaller leakage current than its...
Polymer thin-film transistors (PTFTs) based on MEH-PPV semiconductor are fabricated by spin-coating process and characterized. Gate-bias and drain-bias stress effects at room temperature are observed in the devices. The saturation current decreases and the threshold voltage shifts toward negative direction upon the gate-bias stress. However, the saturation current increases and the threshold voltage...
Pentacene-based organic thin-film transistor (OTFT) with HfO2 as gate dielectric is studied in this work. The HfO2 dielectric was prepared by RF sputtering at room temperature, and subsequently annealed in N2O or NH3 at 200degC. The OTFTs were characterized by IV measurement and 1/f noise measurement. The OTFTs show small threshold voltage and can operate at as low as 3 V. Results indicate that the...
In this brief, a physical model describing the scattering of holes in the channel of SiGe p-MOSFET caused by roughness and charged defects at/near the high- K dielectric/SiO2 interface is proposed. Using the Fang-Howard's variational wave function, the hole mobility is calculated with consideration of the above two scattering mechanisms. The effects of device parameters such as the thicknesses and...
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