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The current SRAM based FPGA, are more and more susceptible to Single Event Upset (SEU) due to Neutron particle interference. The problem is exasperated reducing the CMOS submicronic scale in the manufacturing process, specially for the next generation of SRAM-based FPGAs. Nowadays is common practice for SRAM manufactories to embed fault tolerant mechanisms like Error-Correcting Code schemes in SRAM...
We will present a survey of trends in the semiconductor industry for programmable hardware. The main objective of this paper is educational and the focus is FPGAs and its related or vs technologies which have emerged mostly in the second half of the last decade. We will try to analyze what were the prominent reasons for emerging of these technologies. What are the advantages and drawbacks of them,...
The need of non volatility along with the added flexibility of un limited reprogramming like SRAM has lead to the concept of universal memories. MRAM (magnetoresistive random access memory) is one prominent member of them. At present only Flash is providing a limited bridge for that. Flash based FPGAs have several benefits being non volatile but unfortunately also loose many of the features which...
The past decades have witnessed tremendous research efforts devoted to parallel architectures and programming models for natively computing in space. This resulted in systems which comprise a number of processing units ranging from compact Boolean function generators (FPGAs look-up-tables) to full-fledged microprocessors (MPSoCs). It is often stated in the literature of both areas that performance...
Scalability of architecture, programming model and task control management will be a major challenge for MP-SOC designs in the coming years. The contribution presented in this paper is HS-Scale, a hardware/software framework to study, define and experiment scalable solutions for next generation MP-SOC. The hardware architecture, H-Scale, is a homogeneous MP-SOC based on RISC processors, distributed...
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