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This paper is an investigation of the root causes for changing failure modes in different package types which are subjected to constant JEDEC drop test conditions. Drop test experiments applying memory BGA components show that there is more than one ultimate failure mode and that the failures created in the 2nd level interconnections are dependent on the package type. Thus the package geometry causes...
Virtual prototyping is able to speed-up the development cycle of new products if based on exact models. In case of dynamic mechanical loads like JEDEC drop tests of BGA modules, broken copper traces at the PCB side are more and more often observed to be the ultimate failure effects. Straightforward FEM simulations showed unrealistic high stress and strain results not matching with the experimentally...
This paper deals with the concept of how to integrate results of multi physics investigation of 3D stacks into modern comprehensive 3D data structures. Beside a description of modern 3D data structures and methods for floorplanning and Place&Route, approaches for multi physics modeling are introduced. The extension of the layout optimization process by multi physics modeling is investigated. Finally,...
Physical design algorithms are heavily impacted by the current trend towards 3D integration. This development requires new data structures specifically designed to take 3D-specific constraints into account. There has been rapid development in this field over the last several years. However, it is difficult to compare data structures and evaluate their applicability to new approaches. In this paper,...
Layout design of analog integrated circuits suffers from a lack of automation due to the multitude of complex design constraints. Most of them are specified and considered manually by expert designers (expert knowledge). We present a new methodology that enables the automatic inclusion of expert knowledge in the form of layout constraints. The resulting comprehensive constraint-driven design approach...
Since lead was banned from the solder joints, mechanical tests of microelectronic components and modules have gained much importance not just in mobile electronics but quite in general. The standardized JEDEC drop test is commonly used. It delivers repeatable results for a wide range of loads in the components mounted on the well specified test PCB. As yet the JEDEC drop test is time consuming and...
Layout design of analog and mixed-signal circuits is often a manual and time-consuming, trial-and-error task. Stringent constraints that must be considered simultaneously are a major reason why layout design is often not automated. To overcome this bottleneck in the design process, we present a new constraint-driven design methodology. We have verified our methodology by applying it to the placement...
After surveying the laminate theory, this paper presents a field proven 3-steps concept for modeling printed circuit boards (PCB). First, the behavior of the single plies is studied by means of a 3D detailed model representing a typical cell. Afterwards, the laminate theory is applied to transfer the material data determined in the first step to a 3-layers model, which eventually allows modeling full...
The wiring effort and thus, the routability of electronic designs such as printed circuit boards, multi chip modules and single chip modules largely depends on the assignment of signals to component pins. For modern components that have as many as several thousand pins, this pin assignment cannot be optimized manually. This paper presents four novel pin assignment algorithms that automatically create...
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