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Driven by consumer demand, mobile devices such as smartphones and tablets are offering more desktop-like capabilities. High-performance CPUs and GPUs, which handle compute-intensive tasks, are key to enhancing the user experience in applications such as 3D gaming, high-definition video and internet browsing. A CPU and GPU on a tablet device, however, can together consume up to 90% of the total SoC...
In the advanced CMOS technology nodes, overlap capacitance (Cov), gate fringing capacitance (Cf) and contact-to-gate capacitance (Cctg) have been increasingly important components of transistor parasitic. Accurate Cov could be extract from MOSFET Cgc curve with metal routing de-embedded structure. But Cf and Cctg could not be extracted and separated clearly with traditional AC testkey. Traditionally,...
In this paper we present a Charged-Based Capacitance Measurement (CBCM) cell with an on-chip non-overlapping signal generation circuitry to reduce the number of probe pads, and to enable the test structure to operate at GHz range. Also, we describe the circuit design technique and measurement calibration to improve the resolution limit in 28nm process node. These novel features combine to make it...
Latchup test failures occurred at two IO pins of an IC. Failure analysis revealed damage at the ESD device of a neighboring power pin's ESD protection circuit. To identify the root cause of the problem, the behavior of the ESD circuit in response to the latchup trigger signal was monitored. The ESD protection circuit was found to anomalously respond to even DC-like latchup trigger pulses. A layout...
System-on-a-chip with multiple power domains reduces leakage power consumption by power gating which shut off the idle blocks. Power gating is an effective technology to reduce sub-threshold leakage current. However, without good understanding and careful design, negative effects of power gating may overwhelm the potential gain and make the technique not worth the effort. For example, power gating...
The biggest contributors to the substrate noise are supply noises, since the power and ground wires are directly connected to the silicon substrate for CMOS digital cells. Clock trees in large digital designs can acquire large power consumption when thousands of flip-flops transitioning through the switching zone. Memories also draw significant instantaneous power when being accessed. In this paper,...
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