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Purpose
To estimate the diagnostic accuracy of circumpapillary retinal nerve fibre layer (RNFL) thickness and macular ganglion cell layer–inner plexiform layer (GCL‐IPL) thickness measurements to discriminate an abnormal visual function (i.e. abnormal age‐based visual acuity and/or visual field defect) in children with a newly diagnosed brain tumour.
Methods
This cross‐sectional analysis of a prospective...
An Ultra Low Power (ULP) biomedical System-on Chip (SoC) has been developed for efficient ECG/EEG signal processing in a Body Area Network environment. This experimental SoC explores the use of event-driven peripheral modules that autonomously interact with external sensors together with the use of an Application-Specific-Instruction-set Processor (ASIP) to optimize energy-efficiency during active...
This paper provides an update of the WASP project, which is currently in its third year of execution. WASP project aims at narrowing down the gap between the academic research solutions for wireless sensor networks and their industrial usage. This poster abstract zooms in on two of the project activities namely a low-power traffic aware MAC protocol and a light weight service discovery protocol.
We propose that networks on chip (NOC) are hardwired in field-programmable gate arrays (FPGA). Although some area of the FPGA then has a fixed function, this loss of flexibility is outweighed by the following benefits. First, implementation cost is much reduced. Second, a hardwired NOC solves physical problems such as timing closure and high cost of global wiring. Third, dynamic partial reconfiguration...
A novel routing fabric is introduced that offers high flexibility at significant lower silicon cost compared to routing fabrics currently incorporated in many field programmable gate array (FPGA) devices, IP cores, and IP-core wrappers. The novel fabric is entirely constructed from multiplexers and unidirectional point-to-point connections, controlled by configuration bits, and prove very efficient...
The growth in system-on-chip complexity puts pressure on system verification. Due to limitations in the pre-silicon verification process, errors in hardware and software slip through to the stage when silicon and the complete software stack are first brought together. Finding the remaining errors at this stage is becoming increasing difficult. We propose that debugging should be communication-centric...
The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC). Debugging such SOCs is hard. Based on a classification of debug scope and granularity, we propose that debugging should be communication-centric and based on transactions. Communication-centric debug focuses on the communication...
This paper introduces ASTRA, a novel FPGA-like architecture that can perform operations in space (for maximum performance) or in time (for minimum hardware area) at logic-cell level. Currently, ASTRA is tailored towards DSP applications and supports data flow between nearest neighbor cells. Control signals can be distributed over longer distances using bus-like connections. ASTRA's (logic and interconnect)...
Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size, performance, and/or energy consumption. In this paper, we address the latter bottleneck and propose a novel FPGA interconnect architecture that reduces energy consumption without sacrificing performance and size. It is...
A sulfur-related-pair defect in silicon has been studied with optically detected magnetic resonance spectroscopy. Measurement of the angular dependence of the optically detected magnetic resonance signals supplemented by the analysis of the spectrum "quality" yield to the conclusion that the point group symmetry of the defect studied is C_{1h}.
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