Search results for: U. Heinkel
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In this paper we present an application example for a run-time reconfigurable embedded system. The system design is based on the perceptions of previous works from several groups. We comment on the theoretical background of dynamic reconfiguration with respect to the embedded market and its special needs. Moreover a resource-efficient FPGA system and a first design is presented to serve as a basis...
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This paper describes the implementation of a heterogeneous network node as a reconfigurable application based on embedded ASIC technology. The key points of the paper are the distribution of the reconfiguration data in-band over the network and the in-service-reconfiguration of the network node itself. The node consists of a static ASIC part and three reconfigurable various-grained FPGA-like areas...
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Major challenges that companies face nowadays are extremely volatile markets, a globally distributed supplier network and constantly changing business environments. These circumstances demand a high level of agility and extraordinary flexibility in the business modeling and the organizational structures of a company as well as adaptive and interoperable IT systems. In order to meet these requirements...
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In this paper a low power, 4-bit, 50 MHz flash ADC in 130 nm technology is presented. Power consumption is the most important objective in this ADC. Two blocks, S/H and Latch, can be omitted in this ADC because of the comparator and encoder structures. Flash ADC has a peak SNDR of 23.47 dB at Nyquist frequency while the power consumption is 130 muW with a binary code encoder. This reduces to 115 muW...
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We propose a high level synthesis approach to generate RT level hardware from a specification of operation properties. The property language is called InTerval language (ITL) and we assume the set of properties is complete, such that the properties alone are strong enough to map every possible sequence of input data to exactly one sequence of output data. A major advantage of using operation properties...
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In this paper, we present a prototyping exercise, mapping a turbo decoder high-level description directly to FPGA for fast simulation of a software radio. The turbo decoder algorithm is described in C programming language and the mapping has been done directly using the high level synthesis tool CoDeveloper. The manual transformations made on the code to facilitate efficient compilation and to achieve...
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Formal executable specification is one in the ITRS 2007 design report proposed solution to handle future design challenges. Specifications have to be checked for completeness and consistence. Furthermore, it is desirable to support later design steps by generating descriptions for simulation and synthesis, properties for simulative and formal verification and testing scripts. This can be achieved...
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This paper describes a tool extension named SpecScribe Analog for the specification-driven design of heterogeneous (analog and digital) systems. For SpecScribe a specification consists of atomic items called requirements which can be hierarchically organized. These requirements can be translated to a more implementation like description using components or FSMs. The extension broadens the tool for...
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IEEE Sensors Journal > 2007 > 7 > 5 > 770 - 777
This paper presents an approach for modeling and realization of an inertial navigation system. This system consists of two new 2-D acceleration sensor arrays, three gyroscopes, digital error correction, gravitation compensation, supporting point inclusion, and software application. Modeling is achieved using SystemC-AMS for analog parts and SystemC for digital and software components. The model is...
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Complexity of hardware/software systems is continuously increasing. Formal specification is a methodology to ensure better quality of system specifications and to allow automated verification with tools like model checkers. Many formal specification approaches are known - ranging from programming languages to graphical specification tools. Each approach has its specific benefits. Usually, for abstract...
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An ever increasing portion of design effort is spent on functional verification. The verification space as the set of possible combinations of a design's attributes is likely to be very large making it infeasible to verify each point in this space. State-of-the-art verification tools tackle this problem by using directed random generation of combinations in conjunction with manually defined corner...
