In this paper a low power, 4-bit, 50 MHz flash ADC in 130 nm technology is presented. Power consumption is the most important objective in this ADC. Two blocks, S/H and Latch, can be omitted in this ADC because of the comparator and encoder structures. Flash ADC has a peak SNDR of 23.47 dB at Nyquist frequency while the power consumption is 130 muW with a binary code encoder. This reduces to 115 muW if output data are in Gray code. The proposed ADC achieves 0.1625 pJ per conversion-step if the output is binary.