The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Interlayer cooling removes the heat dissipated by vertically stacked chips in multiple integrated fluid cavities. Its performance scales with the number of dies in the stack and is therefore superior to traditional back-side heat removal. Previous work indicated that pin-fin arrays are ideally suited as through-silicon-via-compatible heat transfer structures. In addition, four-port fluid-delivery...
Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1 cm2. The implementation of 100 μm pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature...
The following study concentrates on two-phase flow boiling of refrigerant R134a inside two similar copper multi-microchannel heat sinks, one of which was designed for singlephase water cooling of microprocessors. The two-phase heat sink was composed of 100 parallel microchannels, 100 μm wide, 680 μm high, 15 mm long with 72 μm-thick fins, and 63 parallel microchannels. Base heat fluxes and channel-based...
Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1 cm2. The implementation of 100 mum pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature...
This article investigates the effect of inlet orifices on saturated critical heat flux (CHF) in multi-microchannel heat sinks. Two different multi-microchannel heat sinks made in copper were tested with three low pressure refrigerants (R134a, R236fa, R245fa). One had 20 parallel rectangular microchannels of 467 times 4052 mum (width times depth) while the other had 29 channels of 199 times 756 mum...
This modeling study is focused on the potential and the limitations of hotspot-adapted liquid heat removal to improve on system pumping power and on the re-usability of output heat, for various packaging schemes at the component level. This is in particular important to improve the power efficiency of datacenters with the consequence to reduce total cost of ownership and their impact on the environment...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.