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Combined measurements of random telegraph noise of drain current and drain current - gate voltage characteristic are employed for determination of field-effect charge carrier mobility in surface channel of nanowire inversion mode and accumulation mode MOSFETs with taking into account parasitic source-drain resistance.
Improvement of current drive in n- and p-type silicon junctionless MOSFETs using strain is demonstrated. The extracted piezoresistance coefficients are in good agreement with the piezoresistive theory and the published coefficients for bulk silicon even for 10 nm-thick silicon nanowires as narrow as 20 nm.
Ultra-scaled Z-RAM cells based on MuGFETs are demonstrated for the first time. Effects of physical parameters such as channel doping concentration, fin width, and gate length on Z-RAM cell performance are discussed. Transient measurements and simulations prove that the basic operational principles are effective on Z-RAM cells with a gate length down to 12.5 nm.
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