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In this paper, we discuss the research and development of several key process modules for realizing high-mobility III-V n-MOSFETs. Interface passivation technologies were developed to realize high quality gate stacks on III-V. InGaAs MOSFETs with in situ doped lattice-mismatched source/drain (S/D) stressors were demonstrated for reduction of S/D series resistance as well as channel strain engineering...
We report the integration of silane and ammonia (SiH4 + NH3) surface passivation technology to realize high-quality gate stack on a high-mobility In0.53Ga0.47As compound semiconductor. Vacuum anneal at 520??C desorbs the native oxide while preserving the surface morphology and material composition of In0.53Ga0.47As. By incorporating SiH4 + NH3 passivation, a thin silicon oxynitride (SiOxNy) interfacial...
In this paper, strained In0.53Ga0.47As MOSFET with SiN liner stressor was demonstrated for the first time. An advanced surface passivation (SiH4+NH3) technology was also employed for achieving good electrical characteristics. The SiN liner stressor gives rise to lateral tensile strain in the channel for significant electron mobility and drive current enhancement. High-stress SiN liner is a promising...
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