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A great deal of effort worldwide is being put into 3-D VLSI development. Wafer stacking is one option for manufacturing, which is good for stacking device wafers of high yield, low heat dissipation, and homogenous materials. However, for applications with moderate yield layers, high power, and differing materials, wafer stacking methods may suffer from cumulative yield issues and potential reliablility...
In this paper, silicon nanocrystals (Si-NCs) fabricated by chemical vapor deposition (CVD) are, for the first time at our knowledge, successfully integrated in a 32 Mb NOR flash memory product, processed in a 130 nm technology platform. The large set of data measured on arrays clearly demonstrates the robustness of our process and integration scheme. Different Si-NC deposition conditions are explored...
In this work, data of a 32Mb Si-NC NOR flash memory product, fabricated in a 130nm ATMEL technology platform have been presented. Measurements have shown an average threshold voltage shift of 3V, without extrinsic bits even after cycling and data retention at 150degC. An in-depth study of gate disturb has been performed, focusing on the influence of the HTO thickness.
This work presents TCAD simulations of NOR NC memories performed with commercial tools, which allow for a good understanding of the impact of the localized charge on both electrostatics and dynamics of the cell. The key role of the position of the trapped charges along the channel length on the threshold voltage shift has been put in evidence. Indeed, this result is critical for NOR discrete-trap...
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