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Reliability characteristics of ZrO2 gate dielectric films on p-GaAs with ultrathin silicon (Si) interfacial passivated layer have been investigated. Results of a systematic study on the impacts of post deposition annealing (PDA) on the physical and electrical properties of RF-sputtered ZrO2 dielectric layers on Si-passivated p-GaAs substrates are reported. The electrical characteristics have been...
Charge trapping kinetics and chemical nature of defects present in Al/TaYOx/strained-Si/Si0.8Ge0.2 MIS capacitors have been studied using internal photoemission and magnetic resonance. Reliability characteristics have been studied using CVS and CCS techniques. Results of electron paramagnetic resonance (EPR) and internal photoemission (IPE) studies on the charge trapping behavior are reported.
Displacement damage mechanisms due to radiation have been investigated and interpreted via abinitio calculation. Effect of radiation-induced Frenkel defect has been incorporated in device modeling. Current voltage characteristics are studied to establish beginning of life (BOL) parameters of the solar cells and the changes that occur due to irradiation (EOL).
Ultra thin (~6-7 nm) silicon-oxynitride films have been deposited on Strained-Si/Si0.8Ge0.2 layers at high temperature of 900degC and 1000degC using rapid thermal nitridation in O2+N2 ambient. The border trap (Qbt) generation using the hysteresis in high-frequency capacitance-voltage (C-V) characteristics under both constant current stressing (CCS) and constant voltage stressing (CVS) has been analyzed...
We demonstrates a complete Technology CAD (TCAD) methodology that addresses the manufacturing challenges posed by rising technological complexity, increasing process variability and shrinking time-to-market windows. Using TCAD simulations as input, Process Compact Models are created to enable efficient analysis of complex and multivariate process-device relationships, with applications to enhancing...
In this paper, the effect of channel implantation dose and energy has been studied for the design of nanoscale FinFET devices for high frequency application. It was observed that the threshold voltage of the device may be increased through both implantation dose and energy but the later is preferable because of less carrier scattering. The drain current and the peak cut-off frequency of the device...
Rapid thermal oxidation (RTO) of heteroepitaxial thin Si1-xGex layers (x=0.85) at 815??C in dry O2 has been studied. We have investigated the origin of interface defects in Si0.15Ge0.85/SiGeO2 RTO oxides by electron paramagnetic resonance (EPR) through internal photoemission (IPE) technique. Spin concentration of the paramagnetic defect centers have been determined from EPR results. After IPE capacitance-voltage...
Effects of electrical stress on DC performance of strain-engineered nMOSFETs are investigated using simulation. The applicability of technology CAD (TCAD) for the prediction of MOSFET reliability is demonstrated.
Drain-induced barrier lowering in substrate-induced strained-Si n-MOSFETs has been investigated. The variation of subthreshold swing as a function of both the gate length and gate to source voltage has also been examined.
Hot carrier reliability of a nanowire Omega-FinFET is investigated for the first time. Hot holes injected into the gate oxide via hot-carrier injection (HCI) at the silicon (Si) - silicon dioxide (SiO2) interface of Omega-FinFETs results in the formation of dangling silicon bonds due to the breaking of silicon-hydrogen bonds and lead to high interface traps generation. The trapping and/or bond breaking...
Meeting performance targets of 22 nm Si- CMOS and beyond, as per 2006 ITRS update, will require innovation at all levels of CMOS development, including new channel materials, device design, integration, circuit design, and system architecture. In new channel materials, some of the options under consideration include (a) local and global strain, (b) Si surface orientation, and (c) non-Si materials...
The performance enhancement in strained-Si n-MOSFETs are evaluated as a function of temperature. Mobility modeling at low temperature is reported. SPICE parameters are extracted for strained-Si n-MOSFETs for the first time.
Device simulation has been used to study the performance enhancement prediction for buried SiGe-channel p-MOSFETs. Steady state self-heating is modeled via the inclusion of thermal-flow analog auxiliary sub-circuits.
In this paper, we demonstrate for the first time via technology computer aided design (TCAD), the enhancement in both the ac and dc performances for process-induced strained-Si MOSFETs over bulk-Si and a comparison of process-induced strained and substrate-induced strained-Si MOSFETs. In addition, we present the hot-electron degradation characteristics for strained-Si n-MOSFETs fabricated in both...
Stacked silicon and zirconium dioxide (SiO 2 /ZrO 2 ) films have been deposited on strained-Si 0.91 Ge 0.09 layer at a low temperature using zirconium tetratert butoxide (ZTB) and ZTB/O 2 in a microwave plasma deposition system. Electrical properties of the as-deposited and annealed (in N 2 at 500 o C) samples have...
Electrical properties of silicon dioxide films deposited on Si at low temperature by microwave plasma enhanced chemical vapour deposition using tetraethylorthosilicate and oxygen have been investigated. Properties of the films deposited on a thin thermal oxide and on an in-situ oxygen plasma treated silicon surface approach those of thermally grown oxide films.<<ETX>>
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