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Statistical fault injection is widely used for analyzing hardware in the presence of soft errors. Although this method can give accurate results for averaged erroneous outcomes with a fairly small sample size, it will not be accurate for vulnerability analysis of each sequential element in the design with small sample sizes. This paper describes a novel and highly efficient technique which is suitable...
Soft errors, caused by radiation, have become a major challenge in today's computer systems and networking equipment, making it imperative that systems be designed to be resilient to errors. Error injection is a powerful approach to evaluate system resilience, and current practice is to inject errors in architectural registers of processors, program variables of applications, or storage elements in...
Choosing the correct error injection technique is of primary importance in simulation-based design and evaluation of robust systems that are resilient to soft errors. Many low-level (e.g., flip-flop-level) error injection techniques are generally used for small systems due to long execution times and significant memory requirements. High-level error injections at the architecture or memory levels...
This paper presents a built-in self repair analyzer with the optimal repair rate for memory arrays with redundancy. The proposed method requires only a single test, even in the worst case. By performing the must-repair analysis on the fly during the test, it selectively stores fault addresses, and the final analysis to find a solution is performed on the stored fault addresses. To enumerate all possible...
At-speed functional testing has proven to be very effective at uncovering defective chips. However for processor testing, generating instruction level tests for covering all faults is a challenge given the issue of scalability. Data-path faults are relatively easier to control and observe compared to control-path faults. In this paper we present a novel method to generate instruction level tests for...
This paper presents an efficient test framework to extend a use of low-cost ATE (Automatic Test Equipment) to at-speed test of high-speed DUT (Device Under Test). To bridge the speed gap between the ATE and the DUT, an off-chip test interface circuit, called Built-off Test Interface (BOTI), has been developed. Unlike the previous methods which use on-chip or off-chip self-test circuits, in our method,...
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