The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Accurate extraction of the parasitic parameters on a printed circuit board (PCB) and establishment of a new design method for high-power density by considering the parasitic components will become major technological issues to increase the power density of converters. This study focuses on the time domain reflectometry (TDR) technique for the effective measurement of parasitic parameters on PCBs with...
A method is proposed for analysis of the attenuation characteristics of electromagnetic interference (EMI) filters for multiple power converters connected to same power line. The analysis results indicate that increase of the conducted EMI noise may occur, because the cut-off frequencies of the EMI-filter are varied according to the number of power converters. A mathematical solution for the cut-off...
Energy Semiconductor Electronics Research Laboratory in AIST has developed an integration design methodology for high power density converters. A part of this work, a novel converter loss estimation method based on power converter platform concept was proposed. The proposed method estimates the converter loss exactly under real circuit operation condition, by taking the correlation among converter...
This paper introduces a 10 A 12 V single chip digitally-controlled DC/DC converter IC based on the low cost 0.6 um BiCD process. This IC includes the digital pulse width modulator (DPWM) module with the dead-time programmability. The average time resolution is 1.22 ns at the clock frequency 25 MHz on 0.6 um process. This resolution is as same as that for the counter-based DPWM with the clock frequency...
The mechanism of common-mode noise current in control and gate-drive circuits on a chopper circuit is discussed. For high power density configurations, common-mode noise current flows not only in the main circuit, but also in the control and gate-drive circuits. This noise current increases the risk of control circuit misoperation, and might flow out from control and gate-drive circuits and interfere...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.