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In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory...
In this work, highly scalable charge trap flash (CTF) memory with bandgap-engineered storage node and vertical channel is proposed. Due to the compact cell layout without individual junction contacts, NAND flash memory has the most suitable architecture for mobile data storage media. In other to achieve even higher integration density, two NAND flash memory cells in the conventional sting are put...
In this work, the reasons for the abnormal corner effect, its impact on the saddle MOSFET device characteristics, and possible approaches to suppress it are examined through simulation. Effectively suppressing the abnormal corner effects is important for application in sub-50 nm high density high performance DRAM cell transistor.
In this paper, we introduce a buried-gate fin and recess channel MOSFET (BG-FiReFET) for a high performance and low power application. The source/drain region in the BG-FiReFET becomes wider than that of the conventional FinFETs without the epi-process. It can alleviate the burden of the high parasitic resistance. We have adopted a buried-gate structure to avoid GIDL current, which has non-overlapped...
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