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As a proposal for the concept of computing using quantum phenomena, we are presenting a system architecture best suited to massively-integrated nano-scale resonant devices. It is a Parzen window classifier which determines the class label of a given input using a number of learned sample data stored in nano devices. The main idea is collecting small bumps made from nano-scale devices having Gaussian-like...
A methodology for building a low-power high-capacity associative system has been developed. In the system, matching cells having bell-shaped I-V characteristics play the role of similarity-evaluation elements and can be replaced by nanoscale quantum-effect devices. The study is aiming to extend the current CMOS designs to the coming era of nano-devices. A multi-core/multi-chip architecture has been...
A feature-based optical flow processor architecture has been developed. It has a special data allocation scheme in on-chip SRAM banks and a parallel shift and matching unit using compact absolute difference circuits. As a result, single-motion-vector/cyclc generation at arbitrary locations in the scene has been achieved. The core circuitries were designed in a 0.18-m 5-metal CMOS technology and sent...
Design and experimental evaluation of power-balanced reconfigurable floating-gate-MOS logic circuit is presented. The circuit can represent all 512 symmetric Boolean functions for eight inputs and 256 Boolean functions for three-input symmetric/asymmetric functions. The programming of function is done by control signals. Namely, no change in hardware configuration is required. The proposed circuit...
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