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In this paper, a low-power Hamming distance associative processor employing time-domain techniques has been developed focusing on the implementation of an r-th nearest-match location identification function. The architecture not only inherits advantages of analog implementations on power consumption but also improves the accuracy of such implementations. This is because it employs digital technique...
A high-frame-rate dense motion vector field generation processor employing an efficient data manipulation scheme has been developed. The computation result of detecting a motion vector (MV) at each pixel location is reused in the adjacent location. As a result, the size of a best-match searching circuitry for MV detection has been reduced to 1/10 of that without data reuse. This allows us to implement...
A directional-edge-feature-based real-time image recognition system has been developed. By employing a digital-pixel-sensor-embedded feature extraction VLSI processor, the delay due to the image data transfer between the image sensor and the feature extraction circuits, the most serious bottleneck in such systems, has been reduced dramatically. Parallel feature vector-generation and template-matching...
A methodology for building a low-power high-capacity associative processor system employing nano functional devices has been proposed. The study is a demonstration of how to use nano-scale devices in building practical applications, particularly in building associative processors. Characteristics of such devices are utilized for similarity evaluation and emulated by a simple NMOS circuitry. The concept...
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