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High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/µm and 1.25mA/µm, and Ieff of 0.95mA/µm and 0.70mA/µm at Ioff =100nA/µm and VDD of 1V, for NFET and PFET,...
For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (LG) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-Vt transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 µA/µm at Ioff = 100 nA/µm for high performance (HP) and 920/880 µA/µm at Ioff = 1 nA/µm for low power (LP), respectively, at VDD = 1 V. High...
We demonstrate the smallest FinFET SRAM cell size of 0.063 μm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation...
Single crystal thin films of the PZT-based ternary perovskite, xPb(Mn,Nb)O3-(1-x)PZT, were fabricated by a magnetron sputtering on (001)MgO substrates. The sputtered thin films were quenched in air after the deposition. The PZT-based thin films exhibited the hard ferroelectric behavior with high piezoelectric coupling factors kt, kt=70%, measured at GHz range FBAR structure. The PZT-based thin films...
GaP is an attractive material for quadratic nonlinear optical devices because of its large nonlinearity, wide transparency range in infrared region, high thermal conductivity and potential for monolithic integration with electronic/photonic semiconductor devices. Very small two-photon absorption coefficient (0.01 cm/GW at 1.064 mum) compared to that of GaAs (25 cm/GW at 1.064 mum) will open up high-power...
Improved sub-10-nm CMOS devices have been investigated by the elevated source/drain extensions (eSDE) using the tunneling silicon selective epitaxial growth (Si-SEG) in the reverse-order source/drain formation. In this eSDE technology, the SEG-Si thickness for eSDE region is precisely controlled by the self-limited Si-SEG process within a narrow slit underneath a SiN sidewall film. Moreover, the SEG-Si...
Rectangular InP corrugations of 70 nm pitch and 40 nm depth were buried with GaInAs by OMVPE so as to preserve the rectangular shape. A low regrowth temperature and short heating up time in an atmosphere of high PH/sub 3/ partial pressure are effective in the suppression of thermal deformation during regrowth.<<ETX>>
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