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This paper presents a new approach on aging sensors for synchronous digital circuits. An adaptive error-prediction flip-flop architecture with built-in aging sensor is proposed, performing on-line monitoring of long-term performance degradation of CMOS digital systems. The main advantage is that the sensor's performance degradation works in favor of the predictive error detection. The sensor is out...
The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented...
The purpose of this paper is to present a new method and structure for the automatic configuration of a digital system to unknown delays in synchronous input data channels. The method makes possible to restore synchronism in node-to-node communication. Synchronism may be lost due to different delays introduced by the various communication channels. The proposed method allows differences in the channel...
In this paper, circuit failure prediction by timing degradation is used to monitor semiconductor aging, which is a safety-critical problem in the automotive market. Reliability and variability issues are worsening with device scaling down. For safe operation, we propose on-chip, on-line aging monitoring. A novel aging sensor (to be selectively inserted in key locations in the design and to be activated...
Electronic systems for safety-critical automotive applications must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is long-term performance degradation due to aging. For safe operation, aging monitoring should be performed on chip, namely using built-in...
In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-faults due to Power-supply disturbances in nanometer technologies. Using a previously proposed VT (power supply Voltage and Temperature)-aware time...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
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